Semiconductor & Computer Engineering
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Difference between revisions of "lake"
| Line 3: | Line 3: | ||
* Intel | * Intel | ||
** Microarchitectures | ** Microarchitectures | ||
| + | *** Edge | ||
| + | **** {{intel|Lakefield|l=arch}} | ||
*** Client | *** Client | ||
**** {{intel|Skylake (client)|Skylake|l=arch}} | **** {{intel|Skylake (client)|Skylake|l=arch}} | ||
| Line 12: | Line 14: | ||
**** {{intel|Cannon Lake|l=arch}} | **** {{intel|Cannon Lake|l=arch}} | ||
**** {{intel|Ice Lake (client)|Ice Lake|l=arch}} | **** {{intel|Ice Lake (client)|Ice Lake|l=arch}} | ||
| − | **** {{intel|Tiger Lake|l=arch}} | + | **** {{intel|Tiger Lake|l=arch}} |
*** Server | *** Server | ||
**** {{intel|Skylake (server)|Skylake|l=arch}} | **** {{intel|Skylake (server)|Skylake|l=arch}} | ||
Revision as of 23:32, 12 May 2019
Lake may refer to:
- Intel
- Microarchitectures
- Edge
- Client
- Server
- MCU
- Cores
- IGPs
- Platforms
- Microarchitectures
- Intel Nervana
 |
This is a disambiguation page used to distinguish between articles with similar names. If an internal link led you here, you may wish to change the link to point directly to the intended article. |