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Difference between revisions of "intel/xeon gold/6238"
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(→‎Cache)
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== Cache ==
 
== Cache ==
 
{{main|intel/microarchitectures/cascade lake#Memory_Hierarchy|l1=Cascade Lake § Cache}}
 
{{main|intel/microarchitectures/cascade lake#Memory_Hierarchy|l1=Cascade Lake § Cache}}
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The Xeon Gold 6238 features a larger non-default 30.25 MiB of L3, a size that would normally be found on an 22-core part.
 
 
{{cache size
 
{{cache size
−
|l1 cache=1.25 MiB
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|l1 cache=1.375 MiB
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|l1i cache=640 KiB
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|l1i cache=704 KiB
−
|l1i break=20x32 KiB
+
|l1i break=22x32 KiB
 
|l1i desc=8-way set associative
 
|l1i desc=8-way set associative
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|l1d cache=640 KiB
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|l1d cache=704 KiB
−
|l1d break=20x32 KiB
+
|l1d break=22x32 KiB
 
|l1d desc=8-way set associative
 
|l1d desc=8-way set associative
 
|l1d policy=write-back
 
|l1d policy=write-back
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|l2 cache=20 MiB
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|l2 cache=22 MiB
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|l2 break=20x1 MiB
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|l2 break=22x1 MiB
 
|l2 desc=16-way set associative
 
|l2 desc=16-way set associative
 
|l2 policy=write-back
 
|l2 policy=write-back

Revision as of 21:23, 7 May 2019

Edit Values
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General Info
Microarchitecture

Xeon Gold 6238 is a 64-bit 22-core x86 high performance server microprocessor introduced by Intel in early 2019. The Gold 6238 is based on the Cascade Lake microarchitecture and is manufactured on a 14 nm process. This chip supports 4-way multiprocessing, sports 2 AVX-512 FMA units as well as three Ultra Path Interconnect links. This microprocessor supports up 1 TiB of hexa-channel DDR4-2933 memory, operates at 2.1 GHz with a TDP of 140 W and features a turbo boost frequency of up to 3.7 GHz.


Cache

Main article: Cascade Lake § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$1.375 MiB
1,408 KiB
1,441,792 B
L1I$704 KiB
720,896 B
0.688 MiB
22x32 KiB8-way set associative 
L1D$704 KiB
720,896 B
0.688 MiB
22x32 KiB8-way set associativewrite-back
L2$22 MiB
22,528 KiB
23,068,672 B
0.0215 GiB
  22x1 MiB16-way set associativewrite-back
L3$30.25 MiB
30,976 KiB
31,719,424 B
0.0295 GiB
  22x1.375 MiB11-way set associativewrite-back
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Facts about "Xeon Gold 6238 - Intel"
RDF feed
full page nameintel/xeon gold/6238 +
instance ofmicroprocessor +
l1$ size1,408 KiB (1,441,792 B, 1.375 MiB) +
l1d$ description8-way set associative +
l1d$ size704 KiB (720,896 B, 0.688 MiB) +
l1i$ description8-way set associative +
l1i$ size704 KiB (720,896 B, 0.688 MiB) +
l2$ description16-way set associative +
l2$ size22 MiB (22,528 KiB, 23,068,672 B, 0.0215 GiB) +
l3$ description11-way set associative +
l3$ size30.25 MiB (30,976 KiB, 31,719,424 B, 0.0295 GiB) +
ldate1900 +