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Difference between revisions of "intel/xeon gold/6254"
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{{intel title|Xeon Gold 6254}}
 
{{intel title|Xeon Gold 6254}}
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{{chip
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{{chip}}
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|future=Yes
 
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|name=Xeon Gold 6254
 
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|image=skylake sp (basic).png
 
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|designer=Intel
 
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|manufacturer=Intel
 
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|model number=6254
 
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|market=Server
 
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|first announced=March, 2019
 
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|first launched=March, 2019
 
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|family=Xeon Gold
 
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|series=6000
 
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|locked=Yes
 
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|frequency=3,100 MHz
 
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|turbo frequency1=4,000 MHz
 
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|bus type=DMI 3.0
 
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|bus links=4
 
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|bus rate=8 GT/s
 
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|clock multiplier=31
 
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|cpuid=0x50655
 
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|isa=x86-64
 
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|isa family=x86
 
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|microarch=Cascade Lake
 
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|platform=Purley
 
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|chipset=Lewisburg
 
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|core name=Cascade Lake SP
 
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|core family=6
 
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|process=14 nm
 
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|technology=CMOS
 
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|word size=64 bit
 
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|core count=18
 
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|thread count=36
 
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|max cpus=4
 
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|tdp=200 W
 
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|package module 1={{packages/intel/fclga-3647}}
 
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}}
 
 
'''Xeon Gold 6254''' is a {{arch|64}} [[18-core]] [[x86]] high performance server microprocessor introduced by [[Intel]] in early [[2019]]. The Gold 6254 is based on the {{intel|Cascade Lake|l=arch}} microarchitecture and is manufactured on a [[14 nm process]]. This chip supports 4-way multiprocessing, sports 2 {{x86|AVX-512}} [[FMA]] units as well as three {{intel|Ultra Path Interconnect}} links. This microprocessor supports up 1 TiB of hexa-channel DDR4-2933 memory, operates at 3.1 GHz with a TDP of 200 W and features a {{intel|turbo boost}} frequency of up to 4 GHz.
 
'''Xeon Gold 6254''' is a {{arch|64}} [[18-core]] [[x86]] high performance server microprocessor introduced by [[Intel]] in early [[2019]]. The Gold 6254 is based on the {{intel|Cascade Lake|l=arch}} microarchitecture and is manufactured on a [[14 nm process]]. This chip supports 4-way multiprocessing, sports 2 {{x86|AVX-512}} [[FMA]] units as well as three {{intel|Ultra Path Interconnect}} links. This microprocessor supports up 1 TiB of hexa-channel DDR4-2933 memory, operates at 3.1 GHz with a TDP of 200 W and features a {{intel|turbo boost}} frequency of up to 4 GHz.
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== Cache ==
 
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{{main|intel/microarchitectures/cascade lake#Memory_Hierarchy|l1=Cascade Lake § Cache}}
 
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{{cache size
 
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|l1 cache=1.125 MiB
 
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|l1i cache=576 KiB
 
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|l1i break=18x32 KiB
 
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|l1i desc=8-way set associative
 
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|l1d cache=576 KiB
 
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|l1d break=18x32 KiB
 
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|l1d desc=8-way set associative
 
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|l1d policy=write-back
 
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|l2 cache=18 MiB
 
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|l2 break=18x1 MiB
 
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|l2 desc=16-way set associative
 
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|l2 policy=write-back
 
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|l3 cache=24.75 MiB
 
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|l3 break=18x1.375 MiB
 
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|l3 desc=11-way set associative
 
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|l3 policy=write-back
 
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}}
 
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== Memory controller ==
 
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{{memory controller
 
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|type=DDR4-2933
 
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|ecc=Yes
 
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|max mem=? GiB
 
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|controllers=2
 
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|channels=6
 
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|max bandwidth=119.21 GiB/s
 
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|bandwidth schan=19.87 GiB/s
 
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|bandwidth dchan=39.74 GiB/s
 
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|bandwidth qchan=79.47 GiB/s
 
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|bandwidth hchan=119.21 GiB/s
 
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}}
 
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== Expansions ==
 
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{{expansions
 
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| pcie revision      = 3.0
 
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| pcie lanes        = 48
 
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| pcie config        = x16
 
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| pcie config 2      = x8
 
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| pcie config 3      = x4
 
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}}
 
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== Features ==
 
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{{x86 features
 
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|real=Yes
 
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|protected=Yes
 
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|smm=Yes
 
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|fpu=Yes
 
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|x8616=Yes
 
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|x8632=Yes
 
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|x8664=Yes
 
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|nx=Yes
 
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|mmx=Yes
 
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|emmx=Yes
 
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|sse=Yes
 
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|sse2=Yes
 
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|sse3=Yes
 
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|ssse3=Yes
 
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|sse41=Yes
 
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|sse42=Yes
 
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|sse4a=No
 
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|avx=Yes
 
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|avx2=Yes
 
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|avx512f=Yes
 
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|avx512cd=Yes
 
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|avx512er=No
 
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|avx512pf=No
 
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|avx512bw=Yes
 
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|avx512dq=Yes
 
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|avx512vl=Yes
 
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|avx512ifma=No
 
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|avx512vbmi=No
 
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|avx5124fmaps=No
 
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|avx512vnni=Yes
 
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|avx5124vnniw=No
 
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|avx512vpopcntdq=No
 
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|abm=Yes
 
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|tbm=No
 
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|bmi1=Yes
 
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|bmi2=Yes
 
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|fma3=Yes
 
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|fma4=No
 
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|aes=Yes
 
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|rdrand=Yes
 
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|sha=No
 
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|xop=No
 
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|adx=Yes
 
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|clmul=Yes
 
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|f16c=Yes
 
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|bfloat16=No
 
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|tbt1=No
 
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|tbt2=Yes
 
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|tbmt3=No
 
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|bpt=No
 
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|eist=Yes
 
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|sst=Yes
 
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|flex=No
 
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|fastmem=No
 
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|ivmd=Yes
 
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|intelnodecontroller=Yes
 
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|intelnode=Yes
 
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|kpt=Yes
 
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|ptt=Yes
 
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|intelrunsure=Yes
 
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|mbe=Yes
 
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|isrt=No
 
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|sba=No
 
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|mwt=No
 
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|sipp=No
 
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|att=No
 
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|ipt=No
 
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|tsx=Yes
 
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|txt=Yes
 
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|ht=Yes
 
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|vpro=Yes
 
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|vtx=Yes
 
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|vtd=Yes
 
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|ept=Yes
 
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|mpx=No
 
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|sgx=No
 
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|securekey=No
 
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|osguard=No
 
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|intqat=No
 
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|dlboost=Yes
 
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|3dnow=No
 
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|e3dnow=No
 
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|smartmp=No
 
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|powernow=No
 
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|amdvi=No
 
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|amdv=No
 
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|amdsme=No
 
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|amdtsme=No
 
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|amdsev=No
 
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|rvi=No
 
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|smt=No
 
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|sensemi=No
 
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|xfr=No
 
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|xfr2=No
 
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|mxfr=No
 
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|amdpb=No
 
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|amdpb2=No
 
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|amdpbod=No
 
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}}
 

Revision as of 20:49, 7 May 2019

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General Info
Microarchitecture

Xeon Gold 6254 is a 64-bit 18-core x86 high performance server microprocessor introduced by Intel in early 2019. The Gold 6254 is based on the Cascade Lake microarchitecture and is manufactured on a 14 nm process. This chip supports 4-way multiprocessing, sports 2 AVX-512 FMA units as well as three Ultra Path Interconnect links. This microprocessor supports up 1 TiB of hexa-channel DDR4-2933 memory, operates at 3.1 GHz with a TDP of 200 W and features a turbo boost frequency of up to 4 GHz.

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