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Hi1610
General Info
DesignerHiSilicon,
ARM Holdings
ManufacturerTSMC
Model NumberHi1610
MarketServer
Introduction2015 (announced)
2015 (launched)
General Specs
FamilyHi16xx
Frequency2,100 MHz
Microarchitecture
ISAARMv8 (ARM)
MicroarchitectureCortex-A57
Core NameCortex-A57
Process16 nm
TechnologyCMOS
Word Size64 bit
Cores16
Threads16
Max Memory128 GiB
Multiprocessing
Max SMP2-Way (Multiprocessor)

Hi1610 is a hexadeca-core 64-bit ARM server microprocessor introduced by HiSilicon in late 2015. Fabricated by TSMC on a 16 nm process, this chip incorporates 16 Cortex-A57 cores operating at 2.1 GHz. The Hi1610 supports up to 128 GiB of dual-channel DDR4-1866 memory.

Cache

Main article: Cortex-A57 § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$1.25 MiB
1,280 KiB
1,310,720 B
L1I$768 MiB
786,432 KiB
805,306,368 B
16x48 KiB8-way set associative 
L1D$512 KiB
524,288 B
0.5 MiB
16x32 KiB8-way set associative 
L2$4 MiB
4,096 KiB
4,194,304 B
0.00391 GiB
  16x256 KiB8-way set associative 
L3$16 MiB
16,384 KiB
16,777,216 B
0.0156 GiB
  16x1 MiB16-way set associative 

Memory controller

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR4-1866
Supports ECCYes
Max Mem256 GiB
Controllers1
Channels2
Width64 bit
Max Bandwidth55.63 GiB/s
56,965.12 MiB/s
59.732 GB/s
59,732.258 MB/s
0.0543 TiB/s
0.0597 TB/s
Bandwidth
Single 13.91 GiB/s
Double 27.81 GiB/s

Expansions

[Edit/Modify Expansions Info]

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Expansion Options
PCIeRevision: 3.0
Max Lanes: 16
Configuration: 2x8

Features

[Edit/Modify Supported Features]

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Supported ARM Extensions & Processor Features
NEONAdvanced SIMD extension
CRC32CRC-32 checksum Extension

Utilizing devices

  • HiSilicon D02

This list is incomplete; you can help by expanding it.

Retrieved from "https://en.wikichip.org/w/index.php?title=hisilicon/kunpeng/hi1610&oldid=89637"
Facts about "Hi1610 - HiSilicon"
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Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
Hi1610 - HiSilicon#pcie +
base frequency2,100 MHz (2.1 GHz, 2,100,000 kHz) +
core count16 +
core nameCortex-A57 +
designerHiSilicon + and ARM Holdings +
familyHi16xx +
first announced2015 +
first launched2015 +
full page namehisilicon/kunpeng/hi1610 +
has ecc memory supporttrue +
instance ofmicroprocessor +
isaARMv8 +
isa familyARM +
l1$ size1,280 KiB (1,310,720 B, 1.25 MiB) +
l1d$ description8-way set associative +
l1d$ size512 KiB (524,288 B, 0.5 MiB) +
l1i$ description8-way set associative +
l1i$ size786,432 KiB (805,306,368 B, 768 MiB) +
l2$ description8-way set associative +
l2$ size4 MiB (4,096 KiB, 4,194,304 B, 0.00391 GiB) +
l3$ description16-way set associative +
l3$ size16 MiB (16,384 KiB, 16,777,216 B, 0.0156 GiB) +
ldate2015 +
manufacturerTSMC +
market segmentServer +
max cpu count2 +
max memory131,072 MiB (134,217,728 KiB, 137,438,953,472 B, 128 GiB, 0.125 TiB) +
max memory bandwidth55.63 GiB/s (56,965.12 MiB/s, 59.732 GB/s, 59,732.258 MB/s, 0.0543 TiB/s, 0.0597 TB/s) +
max memory channels2 +
microarchitectureCortex-A57 +
model numberHi1610 +
nameHi1610 +
process16 nm (0.016 μm, 1.6e-5 mm) +
smp max ways2 +
supported memory typeDDR4-1866 +
technologyCMOS +
thread count16 +
used byHiSilicon D02 +
word size64 bit (8 octets, 16 nibbles) +