Latest revision as of 10:27, 30 April 2019

Carmel is a the successor to Denver 2, an ARM microarchitecture for Nvidia's Tegra series of SoCs.

Process Technology[edit]

Carmel is integrated into chips fabricated on TSMC 12 nm process (12FFN)

Architecture[edit]

Nvidia disclosed very few details regarding Carmel. Carmel is a 10-wide superscalar with each core supporting dual execution mode.

Key changes from Denver 2[edit]

• 12 nm (12FFN)
• ARMv8.2
  • ARM RAS standard support
• Wider dispatch (10, up from 7)

Memory Hierarchy[edit]

• Cache
  • Parity & ECC
  • L1
  • L2
    • 2 MiB
      • Shared per duplex
  • L3
    • 4 MiB
      • Shared by entire cluster
      • Exclusive

Block Diagram[edit]

CPU Complex[edit]

Overview[edit]

Carmel is a CPU microarchitecture designed by Nvidia for their SoCs. The design consists of an 8-core cluster made of 4 core duplexes. The entire complex has cache coherency as well as an I/O coherent memory subsystem which is designed for communication with the various other accelerators on their SoCs such as the vision accelerator, deep learning accelerator, multimedia engine, and the GPU.

The cores consume 500-1,500 mW per core.

Performance claims[edit]

Die[edit]

CPU Complex[edit]

• 8 cores
  • 4 duplexes
  • shared L3
• ~62.25 mm² die size area

CPU Duplex[edit]

• 2 cores
• ~11.4 mm² die size area

Core[edit]

• ~5.75 mm² die size area

Bibliography[edit]

• IEEE Hot Chips 30 Symposium (HCS) 2018.