From WikiChip
Difference between revisions of "phytium/feiteng/ft-2000-64"
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− | {{phytium title|FT-2000 | + | {{phytium title|FT-2000/64}} |
{{chip | {{chip | ||
− | |name=FT-2000 | + | |name=FT-2000/64 |
|no image=Yes | |no image=Yes | ||
|designer=Phytium | |designer=Phytium | ||
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|first launched=2017 | |first launched=2017 | ||
|family=FeiTeng | |family=FeiTeng | ||
− | |series=FT-2000 | + | |series=FT-2000 |
|frequency=2,000 MHz | |frequency=2,000 MHz | ||
|isa=ARMv8.0 | |isa=ARMv8.0 |
Revision as of 14:06, 26 March 2019
Edit Values | |
FT-2000/64 | |
General Info | |
Designer | Phytium |
Manufacturer | TSMC |
Model Number | FT-2000/64 |
Market | Server |
Introduction | 2016 (announced) 2017 (launched) |
General Specs | |
Family | FeiTeng |
Series | FT-2000 |
Frequency | 2,000 MHz |
Microarchitecture | |
ISA | ARMv8.0 (ARM) |
Microarchitecture | Mars I |
Core Name | FTC-660 |
Process | 28 nm |
Technology | CMOS |
Die | 639.576 mm² |
Word Size | 64 bit |
Electrical | |
TDP | 120 W |
Succession | |
FT-2000/64 is a 64 core ARM server SoC designed by Phytium and introduced in 2017. Fabricated on TSMC's 28 nm process, the chip operates at up 2.0 GHz with a TDP of 120 W. This chip is designed for server, communication, and infrastructure applications.
Cache
- Main article: Mars I § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
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Integrated Memory Controller
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Expansions
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Expansion Options
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Facts about "FT-2000/64 - Phytium"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | FT-2000/64 - Phytium#io + |
base frequency | 2,000 MHz (2 GHz, 2,000,000 kHz) + |
core name | FTC-660 + |
designer | Phytium + |
die area | 639.576 mm² (0.991 in², 6.396 cm², 639,576,000 µm²) + |
family | FeiTeng + |
first announced | 2016 + |
first launched | 2017 + |
full page name | phytium/feiteng/ft-2000-64 + |
has ecc memory support | true + |
instance of | microprocessor + |
isa | ARMv8.0 + |
isa family | ARM + |
l1$ size | 4,096 KiB (4,194,304 B, 4 MiB) + |
l1d$ size | 2,048 KiB (2,097,152 B, 2 MiB) + |
l1i$ size | 2,048 KiB (2,097,152 B, 2 MiB) + |
l2$ size | 32 MiB (32,768 KiB, 33,554,432 B, 0.0313 GiB) + |
ldate | 2017 + |
manufacturer | TSMC + |
market segment | Server + |
max memory bandwidth | 95.37 GiB/s (97,658.88 MiB/s, 102.403 GB/s, 102,402.758 MB/s, 0.0931 TiB/s, 0.102 TB/s) + |
max memory channels | 8 + |
max pcie lanes | 33 + |
microarchitecture | Mars I + |
model number | FT-2000/64 + |
name | FT-2000/64 + |
process | 28 nm (0.028 μm, 2.8e-5 mm) + |
series | FT-2000 + |
supported memory type | DDR3-1600 + |
tdp | 120 W (120,000 mW, 0.161 hp, 0.12 kW) + |
technology | CMOS + |
word size | 64 bit (8 octets, 16 nibbles) + |