From WikiChip
Difference between revisions of "intel/xeon gold/6248"
< intel‎ | xeon gold

(6248)
(No difference)

Revision as of 21:44, 3 March 2019

Edit Values
Xeon Gold 6248
skylake sp (basic).png
General Info
DesignerIntel
ManufacturerIntel
Model Number6248
MarketServer
IntroductionMarch, 2019 (announced)
March, 2019 (launched)
ShopAmazon
General Specs
FamilyXeon Gold
Series6000
LockedYes
Frequency2,500 MHz
Turbo Frequency3,900 MHz (1 core)
Bus typeDMI 3.0
Bus rate4 × 8 GT/s
Clock multiplier25
CPUID0x50654
Microarchitecture
ISAx86-64 (x86)
MicroarchitectureCascade Lake
PlatformPurley
ChipsetLewisburg
Core NameCascade Lake SP
Core Family6
Process14 nm
TechnologyCMOS
Word Size64 bit
Cores20
Threads40
Multiprocessing
Max SMP4-Way (Multiprocessor)
Electrical
TDP150 W
Tcase0 °C – 86 °C
TDTS0 °C – 95 °C
Packaging
Template:packages/intel/fclga-3647

Xeon Gold 6248 is a 64-bit 20-core x86 multi-socket high performance server microprocessor to to be introduced by Intel in early 2019. This chip supports up to 4-way multiprocessing. The Gold 6248, which is based on the server configuration of the Skylake microarchitecture and is manufactured on a 14 nm+ process, sports 2 AVX-512 FMA units as well as three Ultra Path Interconnect links. This microprocessor, which operates at 2.5 GHz with a TDP of 150 W and a turbo boost frequency of up to 3.9 GHz, supports up ? GiB of hexa-channel DDR4-2666 ECC memory.

Cache

Main article: Cascade LAke § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$1.25 MiB
1,280 KiB
1,310,720 B
L1I$640 KiB
655,360 B
0.625 MiB
20x32 KiB8-way set associative 
L1D$640 KiB
655,360 B
0.625 MiB
20x32 KiB8-way set associativewrite-back
L2$20 MiB
20,480 KiB
20,971,520 B
0.0195 GiB
  20x1 MiB16-way set associativewrite-back
L3$27.5 MiB
28,160 KiB
28,835,840 B
0.0269 GiB
  20x1.375 MiB11-way set associativewrite-back

Memory controller

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR4-2666
Supports ECCYes
Max Mem? GiB
Controllers2
Channels6
Max Bandwidth119.21 GiB/s
122,071.04 MiB/s
128.001 GB/s
128,000.763 MB/s
0.116 TiB/s
0.128 TB/s
Bandwidth
Single 19.87 GiB/s
Double 39.74 GiB/s
Quad 79.47 GiB/s
Hexa 119.21 GiB/s

Expansions

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIe
Revision3.0
Max Lanes48
Configsx16, x8, x4


Features

[Edit/Modify Supported Features]

Cog-icon-grey.svg
Supported x86 Extensions & Processor Features
MMXMMX Extension
EMMXExtended MMX Extension
SSEStreaming SIMD Extensions
SSE2Streaming SIMD Extensions 2
SSE3Streaming SIMD Extensions 3
SSSE3Supplemental SSE3
SSE4.1Streaming SIMD Extensions 4.1
SSE4.2Streaming SIMD Extensions 4.2
AVXAdvanced Vector Extensions
AVX2Advanced Vector Extensions 2
AVX-512Advanced Vector 512-bit
AVX512FAVX-512 Foundation
AVX512CDAVX-512 Conflict Detection
AVX512BWAVX-512 Byte and Word
AVX512DQAVX-512 Doubleword and Quadword Instructions
AVX512VLAVX-512 Vector Length
ABMAdvanced Bit Manipulation
BMI1Bit Manipulation Instruction Set 1
BMI2Bit Manipulation Instruction Set 2
FMA33-Operand Fused-Multiply-Add
AESAES Encryption Instructions
RdRandHardware RNG
ADXMulti-Precision Add-Carry
CLMULCarry-less Multiplication Extension
F16C16-bit Floating Point Conversion
x86-1616-bit x86
x86-3232-bit x86
x86-6464-bit x86
RealReal Mode
ProtectedProtected Mode
SMMSystem Management Mode
FPUIntegrated x87 FPU
NXNo-eXecute
HTHyper-Threading
TBT 2.0Turbo Boost Technology 2.0
EISTEnhanced SpeedStep Technology
SSTSpeed Shift Technology
TXTTrusted Execution Technology (SMX)
vProIntel vPro
VT-xVT-x (Virtualization)
VT-dVT-d (I/O MMU virtualization)
EPTExtended Page Tables (SLAT)
TSXTransactional Synchronization Extensions
VMDVolume Management Device
NMNode Manager
KPTKey Protection Technology
PTTPlatform Trust Technology
Run SureRun Sure Technology (RAS Capability)
MBE CtrlMode-Based Execute Control
Node CtrlrNode Controller Support
Retrieved from "https://en.wikichip.org/w/index.php?title=intel/xeon_gold/6248&oldid=87020"
Facts about "Xeon Gold 6248 - Intel"
RDF feed
Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
Xeon Gold 6248 - Intel#io +
base frequency2,500 MHz (2.5 GHz, 2,500,000 kHz) +
bus links4 +
bus rate8,000 MT/s (8 GT/s, 8,000,000 kT/s) +
bus typeDMI 3.0 +
chipsetLewisburg +
clock multiplier25 +
core count20 +
core family6 +
core nameCascade Lake SP +
cpuid0x50654 +
designerIntel +
familyXeon Gold +
first announcedMarch 2019 +
first launchedMarch 2019 +
full page nameintel/xeon gold/6248 +
has advanced vector extensionstrue +
has advanced vector extensions 2true +
has advanced vector extensions 512true +
has ecc memory supporttrue +
has extended page tables supporttrue +
has featureAdvanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Vector Extensions 512 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Speed Shift Technology +, Trusted Execution Technology +, Intel vPro Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables + and Transactional Synchronization Extensions +
has intel enhanced speedstep technologytrue +
has intel speed shift technologytrue +
has intel trusted execution technologytrue +
has intel turbo boost technology 2 0true +
has intel vpro technologytrue +
has intel vt-d technologytrue +
has intel vt-x technologytrue +
has locked clock multipliertrue +
has second level address translation supporttrue +
has simultaneous multithreadingtrue +
has transactional synchronization extensionstrue +
has x86 advanced encryption standard instruction set extensiontrue +
instance ofmicroprocessor +
isax86-64 +
isa familyx86 +
l1$ size1,280 KiB (1,310,720 B, 1.25 MiB) +
l1d$ description8-way set associative +
l1d$ size640 KiB (655,360 B, 0.625 MiB) +
l1i$ description8-way set associative +
l1i$ size640 KiB (655,360 B, 0.625 MiB) +
l2$ description16-way set associative +
l2$ size20 MiB (20,480 KiB, 20,971,520 B, 0.0195 GiB) +
l3$ description11-way set associative +
l3$ size27.5 MiB (28,160 KiB, 28,835,840 B, 0.0269 GiB) +
ldateMarch 2019 +
main imageFile:skylake sp (basic).png +
manufacturerIntel +
market segmentServer +
max case temperature359.15 K (86 °C, 186.8 °F, 646.47 °R) +
max cpu count4 +
max dts temperature95 °C +
max memory bandwidth119.21 GiB/s (122,071.04 MiB/s, 128.001 GB/s, 128,000.763 MB/s, 0.116 TiB/s, 0.128 TB/s) +
max memory channels6 +
max pcie lanes48 +
microarchitectureCascade Lake +
min case temperature273.15 K (0 °C, 32 °F, 491.67 °R) +
min dts temperature0 °C +
model number6248 +
nameXeon Gold 6248 +
platformPurley +
process14 nm (0.014 μm, 1.4e-5 mm) +
series6000 +
smp max ways4 +
supported memory typeDDR4-2666 +
tdp150 W (150,000 mW, 0.201 hp, 0.15 kW) +
technologyCMOS +
thread count40 +
turbo frequency (1 core)3,900 MHz (3.9 GHz, 3,900,000 kHz) +
word size64 bit (8 octets, 16 nibbles) +