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Difference between revisions of "arm holdings/microarchitectures/neoverse n1"
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| − | {{armh title| | + | {{armh title|Neoverse N1|arch}} |
{{microarchitecture | {{microarchitecture | ||
|atype=CPU | |atype=CPU | ||
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|designer=ARM Holdings | |designer=ARM Holdings | ||
|manufacturer=TSMC | |manufacturer=TSMC | ||
| − | |introduction=2019 | + | |introduction=February 20, 2019 |
|process=7 nm | |process=7 nm | ||
|oooe=Yes | |oooe=Yes | ||
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|successor link=arm_holdings/microarchitectures/zeus | |successor link=arm_holdings/microarchitectures/zeus | ||
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| − | '''Ares''' is a high-performance [[ARM]] [[microarchitecture]] designed by [[ARM Holdings]] for the server market. This microarchitecture is designed as a synthesizable [[IP core]] and is sold to other semiconductor companies to be implemented in their own chips. | + | '''Neoverse N1''' (codename '''Ares''') is a high-performance [[ARM]] [[microarchitecture]] designed by [[ARM Holdings]] for the server market. This microarchitecture is designed as a synthesizable [[IP core]] and is sold to other semiconductor companies to be implemented in their own chips. |
== History == | == History == | ||
[[File:arm server roadmap techcon 2018.jpg|thumb|right|Arm's server roadmap.]] | [[File:arm server roadmap techcon 2018.jpg|thumb|right|Arm's server roadmap.]] | ||
| − | Ares was first announced by Drew Henry, Arm’s SVP and GM of Infrastructure Business Unit, at his TechCon 2018 keynote. Ares | + | Ares was first announced by Drew Henry, Arm’s SVP and GM of Infrastructure Business Unit, at his TechCon 2018 keynote. Ares was officially unvailed on February 20, 2019. |
== Release Dates == | == Release Dates == | ||
| − | Ares | + | Ares was officially disclosed on February 20, 2019. |
== Process Technology == | == Process Technology == | ||
Revision as of 11:40, 20 February 2019
| Edit Values | |
| Ares µarch | |
| General Info | |
| Arch Type | CPU |
| Designer | ARM Holdings |
| Manufacturer | TSMC |
| Introduction | February 20, 2019 |
| Process | 7 nm |
| Pipeline | |
| OoOE | Yes |
| Speculative | Yes |
| Reg Renaming | Yes |
| Succession | |
Neoverse N1 (codename Ares) is a high-performance ARM microarchitecture designed by ARM Holdings for the server market. This microarchitecture is designed as a synthesizable IP core and is sold to other semiconductor companies to be implemented in their own chips.
History
Ares was first announced by Drew Henry, Arm’s SVP and GM of Infrastructure Business Unit, at his TechCon 2018 keynote. Ares was officially unvailed on February 20, 2019.
Release Dates
Ares was officially disclosed on February 20, 2019.
Process Technology
Ares specifically takes advantage of the power and area advantages of the 7 nm process.
Architecture
 |
Preliminary Data! Information presented in this article deal with future products, data, features, and specifications that have yet to be finalized, announced, or released. Information may be incomplete and can change by final release. |
This list is incomplete; you can help by expanding it.
Bibliography
- Drew Henry keynote, TechCon 2018 keynote.
Facts about "Neoverse N1 - Microarchitectures - ARM"
| codename | Neoverse N1 + |
| core count | 4 +, 8 +, 16 +, 32 +, 64 +, 96 + and 128 + |
| designer | ARM Holdings + |
| first launched | February 20, 2019 + |
| full page name | arm holdings/microarchitectures/neoverse n1 + |
| instance of | microarchitecture + |
| instruction set architecture | ARMv8.2 + |
| manufacturer | TSMC + |
| microarchitecture type | CPU + |
| name | Neoverse N1 + |
| pipeline stages | 11 + |
| process | 7 nm (0.007 μm, 7.0e-6 mm) + |