Semiconductor & Computer Engineering
From WikiChip
Difference between revisions of "intel/microarchitectures/willow cove"
(→Key changes from {{\\|Sunny Cove}}) |
|||
| Line 24: | Line 24: | ||
== Architecture == | == Architecture == | ||
=== Key changes from {{\\|Sunny Cove}}=== | === Key changes from {{\\|Sunny Cove}}=== | ||
| − | {{ | + | * New cache subsystem |
| + | * Security features | ||
| + | {{expand list}} | ||
| + | |||
| + | == Bibliography == | ||
| + | * Intel Architecture Day 2018, December 11, 2018 | ||
Revision as of 19:30, 29 January 2019
| Edit Values | |
| Willow Cove µarch | |
| General Info | |
| Arch Type | CPU |
| Designer | Intel |
| Manufacturer | Intel |
| Introduction | 2020 |
| Process | 10 nm |
| Instructions | |
| ISA | x86-64 |
| Succession | |
Willow Cove is the successor to Sunny Cove, a high-performance 10 nm x86 core microarchitecture designed by Intel for an array of server and client products.
Contents
History
Willow Cove was originally unveiled by Intel at their 2018 architecture day. Willow Cove is intended to succeed Sunny Cove in the 2020 timeframe.
Process Technology
Willow Cove is designed to take advantage of Intel's 10 nm process.
Architecture
Key changes from Sunny Cove
- New cache subsystem
- Security features
This list is incomplete; you can help by expanding it.
Bibliography
- Intel Architecture Day 2018, December 11, 2018
Facts about "Willow Cove - Microarchitectures - Intel"
| codename | Willow Cove + |
| core count | 2 +, 4 +, 6 + and 8 + |
| designer | Intel + |
| first launched | 2020 + |
| full page name | intel/microarchitectures/willow cove + |
| instance of | microarchitecture + |
| instruction set architecture | x86-64 + |
| manufacturer | Intel + |
| microarchitecture type | CPU + |
| name | Willow Cove + |
| pipeline stages (max) | 19 + |
| pipeline stages (min) | 14 + |
| process | 10 nm (0.01 μm, 1.0e-5 mm) + |