From WikiChip
Difference between revisions of "amd/a6/a6-9220c"
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+ | }} | ||
+ | |||
+ | == Features == | ||
+ | {{x86 features | ||
+ | |real=Yes | ||
+ | |protected=Yes | ||
+ | |smm=Yes | ||
+ | |fpu=Yes | ||
+ | |x8616=Yes | ||
+ | |x8632=Yes | ||
+ | |x8664=Yes | ||
+ | |nx=Yes | ||
+ | |mmx=Yes | ||
+ | |emmx=Yes | ||
+ | |sse=Yes | ||
+ | |sse2=Yes | ||
+ | |sse3=Yes | ||
+ | |ssse3=Yes | ||
+ | |sse41=Yes | ||
+ | |sse42=Yes | ||
+ | |sse4a=Yes | ||
+ | |avx=Yes | ||
+ | |avx2=Yes | ||
+ | |avx512f=No | ||
+ | |avx512cd=No | ||
+ | |avx512er=No | ||
+ | |avx512pf=No | ||
+ | |avx512bw=No | ||
+ | |avx512dq=No | ||
+ | |avx512vl=No | ||
+ | |avx512ifma=No | ||
+ | |avx512vbmi=No | ||
+ | |avx5124fmaps=No | ||
+ | |avx5124vnniw=No | ||
+ | |avx512vpopcntdq=No | ||
+ | |abm=Yes | ||
+ | |tbm=No | ||
+ | |bmi1=Yes | ||
+ | |bmi2=Yes | ||
+ | |fma3=Yes | ||
+ | |fma4=No | ||
+ | |aes=Yes | ||
+ | |rdrand=Yes | ||
+ | |sha=Yes | ||
+ | |xop=No | ||
+ | |adx=Yes | ||
+ | |clmul=Yes | ||
+ | |f16c=Yes | ||
+ | |tbt1=No | ||
+ | |tbt2=No | ||
+ | |tbmt3=No | ||
+ | |bpt=No | ||
+ | |eist=No | ||
+ | |sst=No | ||
+ | |flex=No | ||
+ | |fastmem=No | ||
+ | |ivmd=No | ||
+ | |intelnodecontroller=No | ||
+ | |intelnode=No | ||
+ | |kpt=No | ||
+ | |ptt=No | ||
+ | |intelrunsure=No | ||
+ | |mbe=No | ||
+ | |isrt=No | ||
+ | |sba=No | ||
+ | |mwt=No | ||
+ | |sipp=No | ||
+ | |att=No | ||
+ | |ipt=No | ||
+ | |tsx=No | ||
+ | |txt=No | ||
+ | |ht=No | ||
+ | |vpro=No | ||
+ | |vtx=No | ||
+ | |vtd=No | ||
+ | |ept=No | ||
+ | |mpx=No | ||
+ | |sgx=No | ||
+ | |securekey=No | ||
+ | |osguard=No | ||
+ | |intqat=No | ||
+ | |3dnow=No | ||
+ | |e3dnow=No | ||
+ | |smartmp=No | ||
+ | |powernow=No | ||
+ | |amdvi=Yes | ||
+ | |amdv=Yes | ||
+ | |amdsme=No | ||
+ | |amdtsme=No | ||
+ | |amdsev=No | ||
+ | |rvi=No | ||
+ | |smt=Yes | ||
+ | |sensemi=Yes | ||
+ | |xfr=No | ||
+ | |mxfr=No | ||
+ | |amdpb=No | ||
+ | |amdpb2=No | ||
}} | }} |
Revision as of 18:27, 7 January 2019
Edit Values | |
A6-9220C | |
General Info | |
Designer | AMD |
Manufacturer | GlobalFoundries |
Model Number | A6-9220C |
Part Number | AM922CANN23AC |
Market | Mobile |
Introduction | January 6, 2019 (announced) January 6, 2019 (launched) |
Shop | Amazon |
General Specs | |
Family | A6 |
Series | A6-9000 |
Locked | Yes |
Frequency | 1,800 MHz |
Turbo Frequency | 2,700 MHz (1 core) |
Clock multiplier | 18 |
Microarchitecture | |
ISA | x86-64 (x86) |
Microarchitecture | Excavator |
Core Name | Bristol Ridge |
Process | 28 nm |
Technology | CMOS |
Word Size | 64 bit |
Cores | 2 |
Threads | 2 |
Multiprocessing | |
Max SMP | 1-Way (Uniprocessor) |
Electrical | |
TDP | 6 W |
OP Temperature | 0° C – 90 °C |
Packaging | |
Unknown package "amd,socket_fp4" |
A6-9220C is a 64-bit dual-core ultra-low power x86 mobile microprocessor introduced by AMD in early 2019. This processor is based on AMD's Excavator microarchitecture and is fabricated on a 28 nm process. The A6-9220C operates at a base frequency of 1.8 GHz with a TDP of 6 W and a turbo frequency of 2.7 GHz. This APU supports single-channel DDR4-1866 memory and incorporates Radeon R5 series graphics operating at up to 720 MHz.
Cache
- Main article: Excavator § Cache
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
Integrated Memory Controller
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Expansions
Expansion Options |
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Graphics
Integrated Graphics Information
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Features
[Edit/Modify Supported Features]
Supported x86 Extensions & Processor Features
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Facts about "A6-9220C - AMD"