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Difference between revisions of "samsung/exynos/5433"
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|thread count=8
 
|thread count=8
 
|max cpus=1
 
|max cpus=1
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}}
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== Cache ==
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{{main|intel/microarchitectures/coffee_lake#Memory_Hierarchy|l1=Coffee Lake § Cache}}
 +
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Cortex-A57 Cluster:
 +
 +
{{cache size
 +
|l1 cache=320 KiB
 +
|l1i cache=129 KiB
 +
|l1i break=4x48 KiB
 +
|l1d cache=128 KiB
 +
|l1d break=4x32 KiB
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|l2 cache=2 MiB
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|l2 break=1x2 MiB
 +
}}
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Cortex-A53 Cluster:
 +
 +
{{cache size
 +
|l1 cache=256 KiB
 +
|l1i cache=128 KiB
 +
|l1i break=4x32 KiB
 +
|l1d cache=128 KiB
 +
|l1d break=4x32 KiB
 +
|l2 cache=256 KiB
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|l2 break=1x1 256 KiB
 
}}
 
}}
  

Revision as of 15:41, 29 December 2018

Edit Values
Exynos 5433
General Info
DesignerSamsung,
ARM Holdings
ManufacturerSamsung
Model Number5433
MarketMobile
IntroductionSeptember 7, 2014 (announced)
September 7, 2014 (launched)
General Specs
FamilyExynos
SeriesExynos 7
Frequency1,900 MHz, 1,300 MHz
Microarchitecture
ISAARMv8 (ARM)
MicroarchitectureCortex-A57, Cortex-A53
Core NameCortex-A57, Cortex-A53
Process20 nm
TechnologyCMOS
Die113 mm²
Word Size64 bit
Cores8
Threads8
Multiprocessing
Max SMP1-Way (Uniprocessor)

Cache

Main article: Coffee Lake § Cache


Cortex-A57 Cluster:

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$320 KiB
327,680 B
0.313 MiB
L1I$129 KiB
132,096 B
0.126 MiB
4x48 KiB  
L1D$128 KiB
131,072 B
0.125 MiB
4x32 KiB  
L2$2 MiB
2,048 KiB
2,097,152 B
0.00195 GiB
  1x2 MiB  

Cortex-A53 Cluster:

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$256 KiB
262,144 B
0.25 MiB
L1I$128 KiB
131,072 B
0.125 MiB
4x32 KiB  
L1D$128 KiB
131,072 B
0.125 MiB
4x32 KiB  
L2$256 KiB
0.25 MiB
262,144 B
2.441406e-4 GiB
  1x1 256 KiB  

Die

  • Samsung 20 nm process
  • 113 mm² die size
  • Mali-T760 (6 EU)
  • Quad-core Cortex-A53 (small cores)
    • 32 KiB L1I$ and 32 KiB L1D$ per core, and a shared 256 KiB L2
    • 4.4 mm² per cluster
      • ~1 mm² per core
      • ~0.55 mm² for 256 KiB L2 cache
  • Quad-core Cortex-A57 (big cores)
    • 48KB L1I$ and 32KB L1D$ per core, and a shared 2 MiB L2
    • 15.85 mm² per cluster
      • ~3 mm² per core
      • ~3.87 mm² for 2 MiB L2 cache


exynos 5433 die.png

Bibliography

  • Pyo, Jungyul, et al. "23.1 20nm high-K metal-gate heterogeneous 64b quad-core CPUs and hexa-core GPU for high-performance and energy-efficient mobile application processor." Solid-State Circuits Conference-(ISSCC), 2015 IEEE International. IEEE, 2015
Retrieved from "https://en.wikichip.org/w/index.php?title=samsung/exynos/5433&oldid=85362"
Facts about "Exynos 5433 - Samsung"
RDF feed
base frequency1,900 MHz (1.9 GHz, 1,900,000 kHz) + and 1,300 MHz (1.3 GHz, 1,300,000 kHz) +
core count8 +
core nameCortex-A57 + and Cortex-A53 +
designerSamsung + and ARM Holdings +
die area113 mm² (0.175 in², 1.13 cm², 113,000,000 µm²) +
familyExynos +
first announcedSeptember 7, 2014 +
first launchedSeptember 7, 2014 +
full page namesamsung/exynos/5433 +
instance ofmicroprocessor +
isaARMv8 +
isa familyARM +
l1$ size320 KiB (327,680 B, 0.313 MiB) + and 256 KiB (262,144 B, 0.25 MiB) +
l1d$ size128 KiB (131,072 B, 0.125 MiB) +
l1i$ size129 KiB (132,096 B, 0.126 MiB) + and 128 KiB (131,072 B, 0.125 MiB) +
l2$ size2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) + and 0.25 MiB (256 KiB, 262,144 B, 2.441406e-4 GiB) +
ldateSeptember 7, 2014 +
manufacturerSamsung +
market segmentMobile +
max cpu count1 +
microarchitectureCortex-A57 + and Cortex-A53 +
model number5433 +
nameExynos 5433 +
process20 nm (0.02 μm, 2.0e-5 mm) +
seriesExynos 7 +
smp max ways1 +
technologyCMOS +
thread count8 +
word size64 bit (8 octets, 16 nibbles) +