Difference between revisions of "samsung/exynos/5433"

	Edit Values
	Exynos 5433
	General Info
Designer	Samsung,; ARM Holdings
Manufacturer	Samsung
Model Number	5433
Market	Mobile
Introduction	September 7, 2014 (announced); September 7, 2014 (launched)
	General Specs
Family	Exynos
Series	Exynos 7
Frequency	1,900 MHz, 1,300 MHz
	Microarchitecture
ISA	ARMv8 (ARM)
Microarchitecture	Cortex-A57, Cortex-A53
Core Name	Cortex-A57, Cortex-A53
Process	20 nm
Technology	CMOS
Die	113 mm²
Word Size	64 bit
Cores	8
Threads	8
	Multiprocessing
Max SMP	1-Way (Uniprocessor)

Revision as of 05:03, 29 December 2018

Samsung 20 nm process
113 mm² die size
Mali-T760 (6 EU)
Quad-core Cortex-A53 (small cores)
- 32 KiB L1I$ and 32 KiB L1D$ per core, and a shared 256 KiB L2
- 4.4 mm² per cluster
  - ~1 mm² per core
  - ~0.55 mm² for 256 KiB L2 cache
Quad-core Cortex-A57 (big cores)
- 48KB L1I$ and 32KB L1D$ per core, and a shared 2 MiB L2
- 15.85 mm² per cluster
  - ~3 mm² per core
  - ~3.87 mm² for 2 MiB L2 cache

@@ Line 28: / Line 28: @@
 |max cpus=1
 }}
+=== Die ===
+* Samsung [[20 nm process]]
+* 113 mm² die size
+* Mali-T760 (6 EU)
+* Quad-core {{armh|Cortex-A53|l=arch}} ([[small cores]])
+** 32 KiB L1I$ and 32 KiB L1D$ per core, and a shared 256 KiB L2
+** 4.4 mm² per cluster
+*** ~1 mm² per core
+*** ~0.55 mm² for 256 KiB L2 cache
+* Quad-core {{armh|Cortex-A57|l=arch}} ([[big cores]])
+** 48KB L1I$ and 32KB L1D$ per core, and a shared 2 MiB L2
+** 15.85 mm² per cluster
+*** ~3 mm² per core
+*** ~3.87 mm² for 2 MiB L2 cache
+:[[File:exynos 5433 die.png|600px]]