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+ | == Bibliography == | ||
+ | * Mair, Hugh T., et al. "4.3 A 20nm 2.5 GHz ultra-low-power tri-cluster CPU subsystem with adaptive power allocation for optimal mobile SoC performance." Solid-State Circuits Conference (ISSCC), 2016 IEEE International. IEEE, 2016. |
Revision as of 02:49, 29 December 2018
Edit Values | |
MediaTek Helio X20 | |
General Info | |
Designer | MediaTek, ARM Holdings |
Manufacturer | TSMC |
Model Number | Helio X20 |
Part Number | MT6797, MTK6797 |
Market | Mobile, Embedded |
Introduction | May 12, 2015 (announced) March 16, 2016 (launched) |
General Specs | |
Family | Helio |
Series | Helio X |
Frequency | 2,100 MHz, 1,850 MHz, 1,400 MHz |
Bus type | AMBA 4 AXI |
Microarchitecture | |
ISA | ARMv8 (ARM) |
Microarchitecture | Cortex-A53, Cortex-A72 |
Core Name | Cortex-A53, Cortex-A72 |
Process | 20 nm |
Technology | CMOS |
Word Size | 64 bit |
Cores | 10 |
Threads | 10 |
Multiprocessing | |
Max SMP | 1-Way (Uniprocessor) |
Helio X20 (MT6797) is a 64-bit deca-core ARM LTE system on a chip designed by MediaTek and introduced in early 2016. This SoC incorporates 3 independent clusters of cores (called "Tri-Cluster" by MediaTek) operating at varying degrees of performance designed for certain workloads (operating at 1.4 GHz, 1.85 GHz, and 2.1 GHz) and supports up to 6 GiB of dual-channel LPDDR3-1866 memory. This SoC also incorporates a Mali-T800 MP4 IGP operating at 780 MHz. The chip has a modem supporting LTE User Equipment (UE) category 6.
The Helio X20 is identical to Helio X25 except for the lower clocked A72 cores and the lower clocked GPU.
Contents
Architecture
The Helio X20 is designed is composed of 3 individual clusters of CPU cores depending on the level of performance required by the active applications.
- Extreme Performance - 2x Cortex-A72 @ 2.3 GHz
- Performance/Power Balance - 4x Cortex-A53 @ 1.85 GHz
- Power Efficiency - 4x Cortex-A53 @ 1.4 GHz
The three clusters are designed as a modified big.LITTLE configuration.
Cache
- Main articles: Cortex-A53 § Cache and Cortex-A72 § Cache
This section is empty; you can help add the missing info by editing this page. |
Memory controller
Integrated Memory Controller
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Expansions
Expansion Options
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Graphics
Integrated Graphics Information
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Wireless
Wireless Communications | ||||||||||||||||
Wi-Fi | ||||||||||||||||
WiFi |
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2G |
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3G |
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4G |
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Image
- Integrated image signal processor supports 32 MP
- Supports image stabilization
- Supports video stabilization
- Supports noise reduction
- Supports lens shading correction
- Supports AE/AWB/AF
- Supports edge enhancement
- Supports face detection and visual tracking
- Hardware JPEG encoder
Video
- Video encoding 4K2K @ 30fps with H.265 and HDR
- Video decoding 4K2K @ 30fps, h.264, h.265 / HEVC, MPEG-1/2/4, VC-1, VP-8, VP-9
Audio
- Audio content sampling rates 8kHz to 192kHz
- Audio content sampling format 8-bit/16-bit/24-bit Mono/Stereo
- I2S, PCM
- Encode: AMR-NB, AMR-WB, AAC, OGG, ADPCM
- Decode: WAV, MP3, MP2, AAC, AMR-NB, AMR-WB, MIDI, Vorbis, APE, AAC-plus v1, AAC-plus v2, FLAC, WMA, ADPCM
- 7.1 channel MHL output
Utilizing devices
- Alcatel Flash (2017)
- Doogee F7
- Doogee F7 Pro
- Elephone R9
- Elephone S7
- HomTom HT10
- Kodak Ektra
- LeEco Le 2 Pro X620
- LeEco Le 2 X620
- Meizu MX6
- Sharp Z2
- Vernee Apollo Lite
- Xiaomi Redmi Note 4
- Xiaomi Redmi Pro
- Leagoo T10
Bibliography
- Mair, Hugh T., et al. "4.3 A 20nm 2.5 GHz ultra-low-power tri-cluster CPU subsystem with adaptive power allocation for optimal mobile SoC performance." Solid-State Circuits Conference (ISSCC), 2016 IEEE International. IEEE, 2016.
- all microprocessor models
- microprocessor models by mediatek
- microprocessor models by mediatek based on cortex-a53
- microprocessor models by mediatek based on cortex-a72
- microprocessor models by arm holdings
- microprocessor models by arm holdings based on cortex-a53
- microprocessor models by arm holdings based on cortex-a72
- microprocessor models by tsmc