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Difference between revisions of "hisilicon/kunpeng/920-6426"
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'''Hi1620''' is a planned [[octatetraconta-core]] {{arch|64}} [[ARM]] server microprocessor set to be introduced by HiSilicon in late-2018. Fabricated by [[TSMC]] on a [[7 nm process]], this chip incorporates 64 {{armh|Ares|l=arch}} cores operating at up to 3 GHz. The Hi1620 supports up to 1 TiB of octa-channel DDR4-3200 memory.
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[[File:hi1620 exhibit sign.jpg|thumb|right|Hi1620 on exhibit.]]
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'''Hi1620''' is a planned [[octatetraconta-core]] {{arch|64}} [[ARM]] server microprocessor set to be introduced by [[HiSilicon]] in late-2018. Fabricated by [[TSMC]] on a [[7 nm process]], this chip incorporates 64 {{armh|Ares|l=arch}} cores operating at up to 3 GHz with a TDP of up to 200 W. The Hi1620 supports up to 1 TiB of octa-channel DDR4-3200 memory.
  
  

Revision as of 02:40, 16 December 2018

Edit Values
Hi1620
General Info
DesignerHiSilicon,
ARM Holdings
ManufacturerTSMC
Model NumberHi1620
MarketServer
IntroductionSeptember, 2018 (announced)
September, 2018 (launched)
General Specs
FamilyHi16xx
Frequency3,000 MHz
Microarchitecture
ISAARMv8 (ARM)
MicroarchitectureAres
Core NameAres
TechnologyCMOS
Word Size64 bit
Cores48
Threads48
Max Memory512 GiB
Multiprocessing
Max SMP2-Way (Multiprocessor)
Hi1620 on exhibit.

Hi1620 is a planned octatetraconta-core 64-bit ARM server microprocessor set to be introduced by HiSilicon in late-2018. Fabricated by TSMC on a 7 nm process, this chip incorporates 64 Ares cores operating at up to 3 GHz with a TDP of up to 200 W. The Hi1620 supports up to 1 TiB of octa-channel DDR4-3200 memory.


DIL16 Blank.svg Preliminary Data! Information presented in this article deal with a microprocessor or chip that was recently announced or leaked, thus missing information regarding its features and exact specification. Information may be incomplete and can change by final release.


Cache

Main article: Ares § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$8 MiB
8,192 KiB
8,388,608 B
L1I$4 MiB
4,096 KiB
4,194,304 B
64x64 KiB  
L1D$4 MiB
4,096 KiB
4,194,304 B
64x64 KiB  
L2$32 MiB
32,768 KiB
33,554,432 B
0.0313 GiB
  64x512 KiB  
L3$64 MiB
65,536 KiB
67,108,864 B
0.0625 GiB
  64x1 MiB  

Memory controller

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR4-3200
Supports ECCYes
Max Mem1 TiB
Controllers1
Channels8
Width64 bit
Max Bandwidth190.7 GiB/s
195,276.8 MiB/s
204.763 GB/s
204,762.566 MB/s
0.186 TiB/s
0.205 TB/s
Bandwidth
Single 23.84 GiB/s
Double 47.68 GiB/s
Quad 95.37 GiB/s
Octa 190.7 GiB/s

Expansions

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIeRevision: 3.0
Max Lanes: 40
Configuration: x16, x8, x4
USBRevision: 3.0
Max Ports: 4
SATARevision: 3.0
Max Ports: 2

Features

[Edit/Modify Supported Features]

Cog-icon-grey.svg
Supported ARM Extensions & Processor Features
NEONAdvanced SIMD extension
CRC32CRC-32 checksum Extension

Utilizing devices

  • HiSilicon D06

This list is incomplete; you can help by expanding it.

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Facts about "Kunpeng 920-6426 - HiSilicon"
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Kunpeng 920-6426 - HiSilicon#pcie +
base frequency3,000 MHz (3 GHz, 3,000,000 kHz) +
core count48 +
core nameAres +
designerHiSilicon + and ARM Holdings +
familyHi16xx +
first announcedSeptember 2018 +
first launchedSeptember 2018 +
full page namehisilicon/kunpeng/920-6426 +
has ecc memory supporttrue +
instance ofmicroprocessor +
isaARMv8 +
isa familyARM +
l1$ size8,192 KiB (8,388,608 B, 8 MiB) +
l1d$ size4,096 KiB (4,194,304 B, 4 MiB) +
l1i$ size4,096 KiB (4,194,304 B, 4 MiB) +
l2$ size32 MiB (32,768 KiB, 33,554,432 B, 0.0313 GiB) +
l3$ size64 MiB (65,536 KiB, 67,108,864 B, 0.0625 GiB) +
ldate3000 +
manufacturerTSMC +
market segmentServer +
max cpu count2 +
max memory524,288 MiB (536,870,912 KiB, 549,755,813,888 B, 512 GiB, 0.5 TiB) +
max memory bandwidth190.7 GiB/s (195,276.8 MiB/s, 204.763 GB/s, 204,762.566 MB/s, 0.186 TiB/s, 0.205 TB/s) +
max memory channels8 +
max sata ports2 +
max usb ports4 +
microarchitectureAres +
model numberHi1620 +
nameHi1620 +
smp max ways2 +
supported memory typeDDR4-3200 +
technologyCMOS +
thread count48 +
used byHiSilicon D06 +
word size64 bit (8 octets, 16 nibbles) +