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Difference between revisions of "amd/cores/rome"
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| − | '''Rome''' is the codename for [[AMD]]'s high-performance enterprise-level server [[multiprocessors]] based on the {{amd|Zen 2|l=arch}} microarchitecture serving as a successor to {{\\|Naples}}. Rome-based chips are set to be fabricated on | + | '''Rome''' is the codename for [[AMD]]'s high-performance enterprise-level server [[multiprocessors]] based on the {{amd|Zen 2|l=arch}} microarchitecture serving as a successor to {{\\|Naples}}. Rome-based chips are set to be fabricated on TSMC [[7 nm process]]. |
[[File:amd epyc rodmap.png|right|thumb|AMD datacenter roadmap]] | [[File:amd epyc rodmap.png|right|thumb|AMD datacenter roadmap]] | ||
Revision as of 19:39, 20 August 2018
| Edit Values | |
| Rome | |
| General Info | |
| Designer | AMD |
| Manufacturer | TSMC |
| Introduction | May 16, 2017 (announced) |
| Microarchitecture | |
| ISA | x86-64 |
| Microarchitecture | Zen 2 |
| Word Size | 8 octets 64 bit16 nibbles |
| Process | 7 nm 0.007 μm 7.0e-6 mm |
| Technology | CMOS |
| Succession | |
Rome is the codename for AMD's high-performance enterprise-level server multiprocessors based on the Zen 2 microarchitecture serving as a successor to Naples. Rome-based chips are set to be fabricated on TSMC 7 nm process.
See also
 • Power
• Performance |
Facts about "Rome - Cores - AMD"
| designer | AMD + |
| first announced | May 16, 2017 + |
| instance of | core + |
| isa | x86-64 + |
| manufacturer | TSMC + |
| microarchitecture | Zen 2 + |
| name | Rome + |
| process | 7 nm (0.007 μm, 7.0e-6 mm) + |
| technology | CMOS + |
| word size | 64 bit (8 octets, 16 nibbles) + |