Semiconductor & Computer Engineering
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Difference between revisions of "amd/cores/castle peak"
(Castle Peak) |
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Revision as of 10:47, 11 August 2018
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| Castle Peak | |
| General Info | |
| Designer | AMD |
| Introduction | 2019 (announced) 2019 (launched) |
| Microarchitecture | |
| ISA | x86-64 |
| Microarchitecture | Zen 2 |
| Word Size | 8 octets 64 bit16 nibbles |
| Process | 7 nm 0.007 μm 7.0e-6 mm |
| Technology | CMOS |
| Packaging | |
| Package | TR4, FCLGA-4094 (FC-OLGA) |
| Dimension | 75.4 mm 7.54 cm × 58.5 mm2.969 in 5.85 cm × 6.26 mm2.303 in 0.246 in |
| Pitch | 0.87 mm 0.0343 in × 1 mm0.0394 in |
| Contacts | 4094 |
| Socket | TR4, SP3r2, sTR4 |
Castle Peak is codename for AMD's highest-performance enthusiasts microprocessors based on the Zen 2 microarchitecture, serving as a successor to Colfax. Those processors are expected to be fabricated on a 7 nm process.
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Preliminary Data! Information presented in this article deal with future products, data, features, and specifications that have yet to be finalized, announced, or released. Information may be incomplete and can change by final release. |
Facts about "Castle Peak - Cores - AMD"
| designer | AMD + |
| first announced | 2019 + |
| first launched | 2019 + |
| instance of | core + |
| isa | x86-64 + |
| microarchitecture | Zen 2 + |
| name | Castle Peak + |
| package | TR4 + and FCLGA-4094 + |
| process | 7 nm (0.007 μm, 7.0e-6 mm) + |
| socket | TR4 +, SP3r2 + and sTR4 + |
| technology | CMOS + |
| word size | 64 bit (8 octets, 16 nibbles) + |