From WikiChip
Difference between revisions of "hisilicon/kunpeng/hi1612"
< hisilicon‎ | kunpeng

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|max mem=256 GiB
 
|max mem=256 GiB
 
|controllers=1
 
|controllers=1
 +
|channels=4
 +
|width=64 bit
 +
|max bandwidth=63.58 GiB/s
 +
|bandwidth schan=15.89 GiB/s
 +
|bandwidth dchan=31.79 GiB/s
 +
|bandwidth qchan=63.58 GiB/s
 
}}
 
}}

Revision as of 23:50, 31 July 2018

Edit Values
Hi1612
General Info
DesignerHiSilicon,
ARM Holdings
ManufacturerTSMC
Model NumberHi1610
MarketServer
IntroductionJune 4, 2016 (announced)
June 4, 2016 (launched)
General Specs
FamilyHi16xx
Frequency2,100 MHz
Microarchitecture
ISAARMv8 (ARM)
MicroarchitectureCortex-A57
Core NameCortex-A57
TechnologyCMOS
Word Size64 bit
Cores32
Threads32
Multiprocessing
Max SMP1-Way (Uniprocessor)

Hi1612 is a dotriaconta-core 64-bit ARM server microprocessor introduced by HiSilicon in mid-2016. Fabricated by TSMC on a 16 nm process, this chip incorporates 32 Cortex-A57 cores operating at 2.1 GHz. The 1612 supports up to 256 GiB of DDR4-2133 memory.

Cache

Main article: Cortex-A57 § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$2.5 MiB
2,560 KiB
2,621,440 B
L1I$1.5 MiB
1,536 KiB
1,572,864 B
32x48 KiB8-way set associative 
L1D$1 KiB
1,024 B
9.765625e-4 MiB
32x32 KiB8-way set associative 
L2$8 MiB
8,192 KiB
8,388,608 B
0.00781 GiB
  32x256 KiB8-way set associative 
L3$32 MiB
32,768 KiB
33,554,432 B
0.0313 GiB
  32x1 MiB16-way set associative 

Memory controller

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR4-2133
Supports ECCYes
Max Mem256 GiB
Controllers1
Channels4
Width64 bit
Max Bandwidth63.58 GiB/s
65,105.92 MiB/s
68.269 GB/s
68,268.505 MB/s
0.0621 TiB/s
0.0683 TB/s
Bandwidth
Single 15.89 GiB/s
Double 31.79 GiB/s
Quad 63.58 GiB/s
Retrieved from "https://en.wikichip.org/w/index.php?title=hisilicon/kunpeng/hi1612&oldid=80881"
Facts about "Hi1612 - HiSilicon"
RDF feed
base frequency2,100 MHz (2.1 GHz, 2,100,000 kHz) +
core count32 +
core nameCortex-A57 +
designerHiSilicon + and ARM Holdings +
familyHi16xx +
first announcedJune 4, 2016 +
first launchedJune 4, 2016 +
full page namehisilicon/kunpeng/hi1612 +
has ecc memory supporttrue +
instance ofmicroprocessor +
isaARMv8 +
isa familyARM +
l1$ size2,560 KiB (2,621,440 B, 2.5 MiB) +
l1d$ description8-way set associative +
l1d$ size1 KiB (1,024 B, 9.765625e-4 MiB) +
l1i$ description8-way set associative +
l1i$ size1,536 KiB (1,572,864 B, 1.5 MiB) +
l2$ description8-way set associative +
l2$ size8 MiB (8,192 KiB, 8,388,608 B, 0.00781 GiB) +
l3$ description16-way set associative +
l3$ size32 MiB (32,768 KiB, 33,554,432 B, 0.0313 GiB) +
ldateJune 4, 2016 +
manufacturerTSMC +
market segmentServer +
max cpu count1 +
max memory bandwidth63.58 GiB/s (65,105.92 MiB/s, 68.269 GB/s, 68,268.505 MB/s, 0.0621 TiB/s, 0.0683 TB/s) +
max memory channels4 +
microarchitectureCortex-A57 +
model numberHi1610 +
nameHi1612 +
smp max ways1 +
supported memory typeDDR4-2133 +
technologyCMOS +
thread count32 +
word size64 bit (8 octets, 16 nibbles) +