Revision as of 21:31, 24 July 2018

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Kirin 970
General Info
Designer	HiSilicon, ARM Holdings
Manufacturer	TSMC
Model Number	970
Part Number	Hi3670
Market	Mobile
Introduction	September 1, 2017 (announced) September 1, 2017 (launched)
General Specs
Family	Kirin
Series	900
Frequency	1,800 MHz, 2,360 MHz
Microarchitecture
ISA	ARMv8 (ARM)
Microarchitecture	Cortex-A53, Cortex-A73
Core Name	Cortex-A53, Cortex-A73
Process	10 nm
Transistors	5,500,000,000
Technology	CMOS
Die	96.72 mm² 9.75 mm × 9.92 mm
Word Size	64 bit
Cores	8
Threads	8
Max Memory	6 GiB
Multiprocessing
Max SMP	1-Way (Uniprocessor)

Kirin 970 is a 64-bit octa-core high-performance mobile ARM LTE SoC introduced by HiSilicon in mid-2017 at the 2017 IFA. This chip, which is fabricated on a 10 nm process, features four Cortex-A73 big cores operating at up to 2.36 GHz along with four Cortex-A53 little cores operating at up to 1.8 GHz. The 970 incorporates ARM's Mali G72 (12 core) IGP operating at 850 MHz and supports up to 6 GiB of dual-channel LPDDR4-1866 memory.

Overview

Introduced at the 2017 IFA, the overall core organization is identical to the Kirin 960 which was introduced the previous year, but features 20% power efficiency and 40% smaller die area due to the process shrink. The 970 ballooned to over 37.5% more transistors from 4 billion in the 960 to 5.5 billion. The 970 adds many enhancements, including a more powerful Mali G72 GPU and incorporates a new Neural Network Processing Unit (NPU) designed for AI acceleration. The 970 has two improved ISPs and a more powerful LTE modem supporting up to User Equipment (UE) category 18 capable of reaching a maximum downlink of 1.2 Gbps (4x4 MIMO, 256 QAM, 3CC CA).

Cache

Main articles: Cortex-A53 § Cache and Cortex-A73 § Cache

For the Cortex-A73:

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 512 KiB 524,288 B 0.5 MiB L1I$ 256 KiB 262,144 B 0.25 MiB 4x64 KiB     L1D$ 256 KiB 262,144 B 0.25 MiB 4x64 KiB     L2$ 2 MiB 2,048 KiB 2,097,152 B 0.00195 GiB     1x2 MiB

For the Cortex-A53:

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 256 KiB 262,144 B 0.25 MiB L1I$ 128 KiB 131,072 B 0.125 MiB 4x32 KiB     L1D$ 128 KiB 131,072 B 0.125 MiB 4x32 KiB     L2$ 1 MiB 1,024 KiB 1,048,576 B 9.765625e-4 GiB     1x1 MiB

Memory controller

[Edit/Modify Memory Info]

	Integrated Memory Controller
	Max Type LPDDR4-1866 Supports ECC No Max Mem 6 GiB Controllers 1 Channels 2 Width 64 bit Max Bandwidth 27.82 GiB/s 28,487.68 MiB/s 29.871 GB/s 29,871.498 MB/s 0.0272 TiB/s 0.0299 TB/s Bandwidth Single 13.91 GiB/s Double 27.82 GiB/s

Graphics

[Edit/Modify IGP Info]

	Integrated Graphics Information
	GPU Mali-G72 Designer ARM Holdings Execution Units 12 Max Displays 2 Frequency 850 MHz 0.85 GHz 850,000 KHz Output DSI Standards DirectX 12 OpenCL 1.2 OpenGL ES 3.2 OpenVG 1.1 Vulkan 1.0

Wireless

• LTE Modem
  • Up to User Equipment (UE) category 18
    • Downlink of up to 1.2 Gbps (4x4 MIMO, 256 QAM, 3CC CA)
    • Uplink of up to 150 Mbps (2x20MHz CA, 64-QAM)
• Wi-Fi 802.11 ac Dual Band
• Bluetooth 4.2
• NFC
• GPS / A-GPS / GLONASS / BDS

Expansions

• Dual ISPs
  • 14-bit

Neural Network Processing Unit (NPU)

The Kirin 970 incorporates a new Neural Network Processing Unit (NPU) designed specifically to be used as an AI accelerator. According to CEO Richard Yu, who also introduced the processor at 2017 IFA, the NPU uses up the die area of roughly half of the CPU while consuming 50% less power and performing around 25 times faster than a traditional CPU for tasks such as photo recognition. The NPU is said to deliver 1.92 TFLOPs (HP 16-bit) through 256 MAC/cycleS. While the exact architectural details of the NPU have been withheld, the NPU appear to be a licensed IP design from Cambricon Technologies.

Utilizing devices

• Huawei Honor V10 (Honor View 10)
• Huawei Honor 10
• Huawei Mate 10
• Huawei Mate 10 Pro
• Huawei Mate 10 Porsche Design
• Hikey970
• Huawei Honor Play
• Huawei P20
• Huawei P20 Pro
• Huawei Mate RS Porsche Design
• Honor 10
• Huawei Nova 3

This list is incomplete; you can help by expanding it.

Documents

• Hi3670 Data Sheet