Difference between revisions of "intel/core i3/i3-8121u"

	Edit Values
	Core i3-8121U
	General Info
Designer	Intel
Manufacturer	Intel
Model Number	i3-8121U
S-Spec	SRCVC
Market	Mobile
Introduction	May 15, 2018 (announced); May 15, 2018 (launched)
Shop	Amazon
	General Specs
Family	Core i3
Series	i3-8000
Locked	Yes
Frequency	2,200 MHz
Turbo Frequency	3,200 MHz (1 core)
Bus type	OPI
Bus rate	4 GT/s
Clock multiplier	22
CPUID	60663
	Microarchitecture
ISA	x86-64 (x86)
Microarchitecture	Cannon Lake
Core Name	Cannon Lake U
Core Family	6
Core Model	102
Process	10 nm
Technology	CMOS
Word Size	64 bit
Cores	2
Threads	4
Max Memory	32 GiB
	Multiprocessing
Max SMP	1-Way (Uniprocessor)
	Electrical
TDP	15 W
Tjunction	0 °C – 105 °C
Tstorage	-25 °C – 125 °C

Revision as of 16:30, 15 June 2018

Core i3-8121U is a 64-bit dual-core low-end performance x86 mobile microprocessor introduced by Intel in early 2018. This chip is fabricated on Intel's 10 nm process and is based on the Cannon Lake microarchitecture. The i3-8121U has a base frequency of 2.2 GHz with a TDP of 15 Watts and a turbo boost of 3.2 GHz. This chip supports up to 32 GiB of dual-channel DDR4/LPDDR4X-2400 memory and has no integrated graphics processor.

Preliminary Data! Information presented in this article deal with a microprocessor or chip that was recently announced or leaked, thus missing information regarding its features and exact specification. Information may be incomplete and can change by final release.

Cache

Main article: Cannon Lake § Cache

[Edit/Modify Cache Info]

Cache Organization

Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.

L1$

128 KiB

131,072 B
0.125 MiB

L1I$	64 KiB 65,536 B 0.0625 MiB	2x32 KiB	8-way set associative
L1D$	64 KiB 65,536 B 0.0625 MiB	2x32 KiB	8-way set associative	write-back

L2$

512 KiB

0.5 MiB
524,288 B
4.882812e-4 GiB

		2x256 KiB	4-way set associative	write-back

L3$

4 MiB

4,096 KiB
4,194,304 B
0.00391 GiB

			16-way set associative	write-back

Memory controller

[Edit/Modify Memory Info]

Integrated Memory Controller

Max Type	DDR4-2400, LPDDR4-2400, LPDDR4X-2400
Supports ECC	No
Controllers	1
Channels	2
Max Bandwidth	35.76 GiB/s 36,618.24 MiB/s 38.397 GB/s 38,397.008 MB/s 0.0349 TiB/s 0.0384 TB/s
Bandwidth	Single 17.88 GiB/s Double 35.76 GiB/s

Expansions

[Edit/Modify Expansions Info]

Expansion Options

PCIe	Revision: 3.0
	Max Lanes: 16
	Configuration: 1x4, 2x2, 1x2+2x1, 4x1

Graphics

This chip has no integrated graphics processor.

Features

[Edit/Modify Supported Features]

Supported x86 Extensions & Processor Features

MMX	MMX Extension
EMMX	Extended MMX Extension
SSE	Streaming SIMD Extensions
SSE2	Streaming SIMD Extensions 2
SSE3	Streaming SIMD Extensions 3
SSSE3	Supplemental SSE3
SSE4.1	Streaming SIMD Extensions 4.1
SSE4.2	Streaming SIMD Extensions 4.2
AVX	Advanced Vector Extensions
AVX2	Advanced Vector Extensions 2
AVX-512	Advanced Vector 512-bit
AVX512F	AVX-512 Foundation
AVX512CD	AVX-512 Conflict Detection
AVX512BW	AVX-512 Byte and Word
AVX512DQ	AVX-512 Doubleword and Quadword Instructions
AVX512VL	AVX-512 Vector Length
AVX512_IFMA	AVX-512 Integer Fused Multiply-Add
AVX512_VBMI	AVX-512 Vector Bit Manipulation Instructions
ABM	Advanced Bit Manipulation
BMI1	Bit Manipulation Instruction Set 1
BMI2	Bit Manipulation Instruction Set 2
FMA3	3-Operand Fused-Multiply-Add
AES	AES Encryption Instructions
RdRand	Hardware RNG
SHA	SHA Extensions
ADX	Multi-Precision Add-Carry
CLMUL	Carry-less Multiplication Extension
F16C	16-bit Floating Point Conversion

x86-16	16-bit x86
x86-32	32-bit x86
x86-64	64-bit x86
Real	Real Mode
Protected	Protected Mode
SMM	System Management Mode
FPU	Integrated x87 FPU
NX	No-eXecute
HT	Hyper-Threading
TBT 2.0	Turbo Boost Technology 2.0
EIST	Enhanced SpeedStep Technology
SST	Speed Shift Technology
VT-x	VT-x (Virtualization)
VT-d	VT-d (I/O MMU virtualization)
EPT	Extended Page Tables (SLAT)
MPX	Memory Protection Extensions
SGX	Software Guard Extensions
Secure Key	Secure Key Technology
SMEP	OS Guard Technology
Flex Memory	Flex Memory Access
ISRT	Smart Response Technology
MWT	My WiFi Technology
IPT	Identity Protection Technology

@@ Line 60: / Line 60: @@
 |l2 policy=write-back
 |l3 cache=4 MiB
-|l3 break=2x2 MiB
 |l3 desc=16-way set associative
 |l3 policy=write-back

Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.	Core i3-8121U - Intel#pcie +
base frequency	2,200 MHz (2.2 GHz, 2,200,000 kHz) +
bus rate	4,000 MT/s (4 GT/s, 4,000,000 kT/s) +
bus type	OPI +
clock multiplier	22 +
core count	2 +
core family	6 +
core model	102 +
core name	Cannon Lake U +
cpuid	60663 +
designer	Intel +
family	Core i3 +
first announced	May 15, 2018 +
first launched	May 15, 2018 +
full page name	intel/core i3/i3-8121u +
has advanced vector extensions	true +
has advanced vector extensions 2	true +
has advanced vector extensions 512	true +
has ecc memory support	false +
has extended page tables support	true +
has feature	Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Vector Extensions 512 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Speed Shift Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables +, Memory Protection Extensions +, Software Guard Extensions +, Secure Key Technology +, OS Guard +, Flex Memory Access +, Smart Response Technology +, My WiFi Technology + and Identity Protection Technology +
has intel enhanced speedstep technology	true +
has intel flex memory access support	true +
has intel identity protection technology support	true +
has intel my wifi technology support	true +
has intel secure key technology	true +
has intel smart response technology support	true +
has intel speed shift technology	true +
has intel supervisor mode execution protection	true +
has intel turbo boost technology 2 0	true +
has intel vt-d technology	true +
has intel vt-x technology	true +
has locked clock multiplier	true +
has second level address translation support	true +
has simultaneous multithreading	true +
has x86 advanced encryption standard instruction set extension	true +
instance of	microprocessor +
isa	x86-64 +
isa family	x86 +
l1$ size	128 KiB (131,072 B, 0.125 MiB) +
l1d$ description	8-way set associative +
l1d$ size	64 KiB (65,536 B, 0.0625 MiB) +
l1i$ description	8-way set associative +
l1i$ size	64 KiB (65,536 B, 0.0625 MiB) +
l2$ description	4-way set associative +
l2$ size	0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) +
l3$ description	16-way set associative +
l3$ size	4 MiB (4,096 KiB, 4,194,304 B, 0.00391 GiB) +
ldate	May 15, 2018 +
manufacturer	Intel +
market segment	Mobile +
max cpu count	1 +
max junction temperature	378.15 K (105 °C, 221 °F, 680.67 °R) +
max memory	32,768 MiB (33,554,432 KiB, 34,359,738,368 B, 32 GiB, 0.0313 TiB) +
max memory bandwidth	35.76 GiB/s (36,618.24 MiB/s, 38.397 GB/s, 38,397.008 MB/s, 0.0349 TiB/s, 0.0384 TB/s) +
max memory channels	2 +
max storage temperature	398.15 K (125 °C, 257 °F, 716.67 °R) +
microarchitecture	Cannon Lake +
min junction temperature	273.15 K (0 °C, 32 °F, 491.67 °R) +
min storage temperature	248.15 K (-25 °C, -13 °F, 446.67 °R) +
model number	i3-8121U +
name	Core i3-8121U +
process	10 nm (0.01 μm, 1.0e-5 mm) +
s-spec	SRCVC +
series	i3-8000 +
smp max ways	1 +
supported memory type	DDR4-2400 +, LPDDR4-2400 + and LPDDR4X-2400 +
tdp	15 W (15,000 mW, 0.0201 hp, 0.015 kW) +
technology	CMOS +
thread count	4 +
turbo frequency (1 core)	3,200 MHz (3.2 GHz, 3,200,000 kHz) +
word size	64 bit (8 octets, 16 nibbles) +
x86/has memory protection extensions	true +
x86/has software guard extensions	true +

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