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Difference between revisions of "risc-v/microarchitectures"
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| [[Esperanto]] || RV64GC || {{esperanto|ET-Minion|l=arch}}, {{esperanto|ET-Maxion|l=arch}} | | [[Esperanto]] || RV64GC || {{esperanto|ET-Minion|l=arch}}, {{esperanto|ET-Maxion|l=arch}} | ||
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− | | [[Microsemi]] || RV32IMA | + | | [[Microsemi]] || RV32IMA/F || {{microsemi|Mi-V|l=arch}} |
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| [[Nvidia]] || RV64I || {{nvidia|NV-RISCV|l=arch}} | | [[Nvidia]] || RV64I || {{nvidia|NV-RISCV|l=arch}} |
Revision as of 09:11, 17 April 2018
RISC-V
Instruction Set Architecture
Instruction Set Architecture
General
Base Variants(base)
Standard Extensions(all)
Topics
- Foundation
- Non-Standard Extensions
- Addressing Modes
- Registers
- Assembly
- Interrupts
- Microarchitectures
Various microarchitectures have been designed for RISC-V by a number of companies. Below is a list of those microarchitectures.
List of RISC-V microarchitectures
Designer | ISA | Microarchitectures |
---|---|---|
SiFive | RV32IMAC | E31 |
RV64IMAC | E51 | |
RV64GC | E54-MC | |
Andes | RV32IMAC | N25 |
Esperanto | RV64GC | ET-Minion, ET-Maxion |
Microsemi | RV32IMA/F | Mi-V |
Nvidia | RV64I | NV-RISCV |
Codasip | RV32E | CODIX-BK1 |
RV32E, RV32I | CODIX-BK3 | |
RV32I/RV64I | CODIX-BK5 |