Semiconductor & Computer Engineering
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Difference between revisions of "intel/microarchitectures/tiger lake"
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|process=10 nm | |process=10 nm | ||
|isa=x86-64 | |isa=x86-64 | ||
| − | + | |predecessor=Ice Lake | |
| − | |predecessor= | + | |predecessor link=intel/microarchitectures/ice lake |
| − | |predecessor link=intel/microarchitectures/ | + | |successor=Alder Lake |
| − | |successor=Sapphire Rapids | + | |successor link=intel/microarchitectures/alder lake |
| − | | | + | |contemporary=Sapphire Rapids |
| + | |contemporary link=intel/microarchitectures/sapphire rapids | ||
|succession=Yes | |succession=Yes | ||
}} | }} | ||
Revision as of 22:41, 5 April 2018
| Edit Values | |
| Tigerlake µarch | |
| General Info | |
| Arch Type | CPU |
| Designer | Intel |
| Manufacturer | Intel |
| Introduction | 2019 |
| Process | 10 nm |
| Instructions | |
| ISA | x86-64 |
| Succession | |
| Contemporary | |
| Sapphire Rapids | |
Tigerlake (TGL) is a planned microarchitecture by Intel as a successor to Icelake. Tigerlake is expected to be fabricated using a 10 nm process. Tigerlake is the "Optimization" microarchitecture as part of Intel's PAO model.
Process Technology
- Main article: Cannon Lake § Process Technology
Tigerlake is set to use the same 10 nm process that was designed for Cannon Lake.
Architecture
Not much is known about Tigerlake's architecture.
Key changes from Icelake
 |
Preliminary Data! Information presented in this article deal with future products, data, features, and specifications that have yet to be finalized, announced, or released. Information may be incomplete and can change by final release. |
See also
Facts about "Tiger Lake - Microarchitectures - Intel"
| codename | Tigerlake + |
| designer | Intel + |
| first launched | 2019 + |
| full page name | intel/microarchitectures/tiger lake + |
| instance of | microarchitecture + |
| instruction set architecture | x86-64 + |
| manufacturer | Intel + |
| microarchitecture type | CPU + |
| name | Tigerlake + |
| process | 10 nm (0.01 μm, 1.0e-5 mm) + |