Revision as of 23:47, 29 March 2018

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Exynos 9610
General Info
Designer	Samsung, ARM Holdings
Manufacturer	Samsung
Model Number	9610
Market	Mobile
Introduction	March 22, 2018 (announced) October, 2018 (launched)
General Specs
Family	Exynos
Series	Exynos 7
Frequency	2,300 MHz, 1,600 MHz
Microarchitecture
ISA	ARMv8 (ARM)
Microarchitecture	Cortex-A73, Cortex-A53
Core Name	Cortex-A73, Cortex-A53
Process	10 nm
Technology	CMOS
Word Size	64 bit
Cores	8
Threads	8
Multiprocessing
Max SMP	1-Way (Uniprocessor)

Exynos 9610 is a 64-bit ARM mid-range microprocessor designed by Samsung set to launch in late 2018. Manufactured on Samsung's 10 nm process, the 9610 features eight cores consisting of four Cortex-A73 big cores operating at up to 2.3 GHz and four Cortex-A53 little cores operating at up to 1.6 GHz. This processor incorporates a Mali-G72 MP3 GPU and supports up to 4 GiB of quad-channel LPDDR4x-3200 memory. This chip incorporates an LTE modem supporting Cat 12 600Mbps download and Cat 13 150Mbps upload as well as 802.11ac, Bluetooth 5.0, and a 24 MP ISP.

Preliminary Data! Information presented in this article deal with a microprocessor or chip that was recently announced or leaked, thus missing information regarding its features and exact specification. Information may be incomplete and can change by final release.

Cache

Main articles: Cortex-A73 § Cache and Cortex-A55 § Cache

For the Cortex-A73 core cluster:

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

For the Cortex-A55 cluster:

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

Memory controller

[Edit/Modify Memory Info]

	Integrated Memory Controller
	Max Type LPDDR4X-3200 Supports ECC No Max Mem 6 GiB Frequency 1600 MHz Controllers 4 Channels 4 Width 16 bit Bandwidth Single 2.98 GiB/s Double 5.96 GiB/s Quad 11.92 GiB/s

Graphics

[Edit/Modify IGP Info]

	Integrated Graphics Information
	GPU Mali-G72 Designer ARM Holdings Execution Units 3 Max Displays 2 Frequency ? MHz "? MHz" is not a number. Output DSI Standards DirectX 12 OpenCL 2 OpenGL ES 3.2 OpenVG 1.1 Vulkan 1.0

Wireless

Wireless Communications
Cellular
4G	LTE Advanced UE Cat DL 12 (600 Mbps) UE Cat UL 13 (150 Mbps)

ISP

• 24MP Rear
• 24MP Front
• 16MP+16MP Dual

Features

[Edit/Modify Supported Features]

	Supported ARM Extensions & Processor Features
	NEON Advanced SIMD extension CRC32 CRC-32 checksum Extension Crypto Cryptographic Extension FP Floating-point Extension

Utilizing devices

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