Revision as of 16:08, 8 March 2018

Intel's mesh interconnect architecture is a multi-core system interconnect architecture that implements a 2-dimensional array of half rings. Their mesh architecture has replaced the ring interconnect architecture in the server and HPC markets.

History

Since the late 2000s, Intel has used a ring interconnect architecture in order to interconnect multiple physical cores together efficiently. Throughout the 2010s as the number of cores on Intel's high-end models continue to increase, the ring reached fairly problematic scaling issues, particularly in the area of bandwidth and latency. To significant mitigate those bottlenecks, Intel introduced a new mesh interconnect architecture which implemented a mesh networking topology in order to reduce the latency between nodes and increase the bandwidth.

In June 2016, Intel launched new Xeon Phi MIC microprocessors based on Knights Landing which was Intel's first microarchitecture to implement the new interconnect architecture. In mid-2017 Intel launched the Skylake server microarchitecture which featured also featured the mesh interconnect. This microarchitecture is found in their server (Xeon Scalable) microprocessors and the Core i7 and Core i9 HEDT parts.

Overview

Intel's mesh interconnect architecture consists of a number of tightly coupled concepts:

• Mesh - the fabric, a 2-dimensional array of half rings forming a system-wide interconnect grid
• Tile - a modular IP block that can be replicated multiple times across a large grid
  • Core Tile - a specific kind of tile that incorporates an Intel's x86 core
  • IMC Tile - a specific kind of tile that incorporates an integrated memory controller
• Caching/Home Agent (CHA) - a unit found inside the core tiles that maintains the cache coherency between tiles. The CHA also interfaces with the CMS
• Converged/Common Mesh Stop (CMS) - A mesh stop station, facilitating the interface between a tile and the fabric

General Floorplan

Below is the general floorplan.

Tiles are replicated in the X and Y axis as many times as desired. Each tile is associated with its own CMS which allows the tile to interface with the mesh.

References

• IEEE Hot Chips 27 Symposium (HCS) 2015.
• IEEE ISSCC 2018