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There are 128 neuromorphic cores, each containing a "learning engine" that can be programmed to adopt to the network parameters during operation such as the spike timings and their impact. This makes the chip more flexible as it allows various paradigms such as supervisor/non-supervisor and reinforcing/reconfigurablity without requiring any particular approach. The choice for higher flexibility is intentional in order to defer various architectural decisions that could be detrimental to research.
 
There are 128 neuromorphic cores, each containing a "learning engine" that can be programmed to adopt to the network parameters during operation such as the spike timings and their impact. This makes the chip more flexible as it allows various paradigms such as supervisor/non-supervisor and reinforcing/reconfigurablity without requiring any particular approach. The choice for higher flexibility is intentional in order to defer various architectural decisions that could be detrimental to research.
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==== Neural Unit ====
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Loihi implements a variant of the [[current-based synapse]] (CUBA) [[leaky integrate-and-fire neuron]] model with two internal state variables:
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* Synaptic response current <math>u_i(t)</math> - the weighted sum of the input spikes and a constant bias
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* Membrane potential <math>v_t(t)</math> - a leaky (i.e. weakens over time) spike potential function that sends out a spike when the potential passes the firing threshold
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It's worth noting that since Loihi is a digital architecture, the above  continuous functions are approximated using discrete a timestep whereby all neurons maintain a timestemp synchronized throughout the entire chip. This is needed in order to enable well-defined behaviors.
  
 
:[[File:loihi spikes.gif|400px]]
 
:[[File:loihi spikes.gif|400px]]

Revision as of 23:41, 1 March 2018

Edit Values
Loihi
General Info
DesignerIntel
ManufacturerIntel
MarketArtificial Intelligence
IntroductionSeptember 25, 2017 (announced)
January, 2018 (launched)
ShopAmazon
Microarchitecture
Process14 nm
Transistors2,070,000,000
TechnologyCMOS
Die60 mm²
Vcore0.50 V-1.25 V

Loihi (pronounced low-ee-hee) is a neuromorphic research test chip designed by Intel Labs that uses a asynchronous spiking neural network (SNN) to implement adaptive self-modifying event-driven fine-grained parallel computations used to implement learning and inference with high efficiency. The chip is a 128-neuromorphic cores many-core IC fabricated on Intel's 14 nm process.

The chip is named after the Loihi as a play-on-words - Loihi is an emerging Hawaiian submarine volcano that is set to surface one day.

Overview

Announced in September 2017, Loihi is predominantly a research chip meaning performance characteristics are not guaranteed. Loihi consists of a asynchronous spiking neural network (SNN) meaning instead of manipulating signals, the chip sends spikes along activate synapses. Connections are asynchronous and highly timed based. Neuromorphic cores containing many neurons are interlinked and receive spikes from elsewhere in the network. When received spikes accumulate for a certain period of time and reach a set threshold, the core will fire off its own spikes to its connected neurons. Preceding spikes reinforce each other and the neuron connections while spikes that follows will inhibit the connection, declining the connectivity until all activities are halted.

architecture

intel loihi many-core neural mesh.png

The chip itself implements of a fully asynchronous many-core mesh of 128 neuromorphic cores. It implements a spiking neural network (SNN) whereby at any given time one or more of the implemented neurons may send out an impulse (i.e., spike) to its neighbors though the directed links (synapses). All neurons have a local state with their own set of rules that affects their evolution and the timing of spike generation. Interaction is entirely asynchronous, sporadic, and independent of any other neuron on the network.

There are 128 neuromorphic cores, each containing a "learning engine" that can be programmed to adopt to the network parameters during operation such as the spike timings and their impact. This makes the chip more flexible as it allows various paradigms such as supervisor/non-supervisor and reinforcing/reconfigurablity without requiring any particular approach. The choice for higher flexibility is intentional in order to defer various architectural decisions that could be detrimental to research.

Neural Unit

Loihi implements a variant of the current-based synapse (CUBA) leaky integrate-and-fire neuron model with two internal state variables:

  • Synaptic response current Equation u Subscript i Baseline left-parenthesis t right-parenthesis - the weighted sum of the input spikes and a constant bias
  • Membrane potential Equation v Subscript t Baseline left-parenthesis t right-parenthesis - a leaky (i.e. weakens over time) spike potential function that sends out a spike when the potential passes the firing threshold

It's worth noting that since Loihi is a digital architecture, the above continuous functions are approximated using discrete a timestep whereby all neurons maintain a timestemp synchronized throughout the entire chip. This is needed in order to enable well-defined behaviors.

loihi spikes.gif

The chip was initially tested and simulated using FPGAs. Actual silicon implementations arrived in late November. Loihi is fabricated on Intel's 14 nm process and has a total of 130,000 artificial neurons and 130 million synapses. In addition to the 128 neuromorphic cores, there are 3 managing Lakemont cores.

Die

Floorplan
  • 14 nm process
  • 2,070,000,000 transistors
    • 128 neuromorphic cores + 3 x86 cores
  • 60 mm² die size
intel loihi die shot.png

References

  • Jim Held, Intel Fellow & Director Emerging Technologies Research, Intel Labs, HPC Developer Conference 2017 ("Leading The Evolution of Compute: Neuromorphic and Quantum Computing").

See also

Facts about "Loihi - Intel"
back imageFile:loihi (back).png +
core voltage (max)1.25 V (12.5 dV, 125 cV, 1,250 mV) +
core voltage (min)0.5 V (5 dV, 50 cV, 500 mV) +
designerIntel +
die area60 mm² (0.093 in², 0.6 cm², 60,000,000 µm²) +
first announcedSeptember 25, 2017 +
first launchedJanuary 2018 +
full page nameintel/loihi +
instance ofneuromorphic chip +
ldateJanuary 2018 +
main imageFile:loihi (front).png +
manufacturerIntel +
market segmentArtificial Intelligence +
max cpu count16,384 +
nameLoihi +
neuron count131,072 +
process14 nm (0.014 μm, 1.4e-5 mm) +
smp max ways16,384 +
synapse count130,000,000 +
technologyCMOS +
transistor count2,070,000,000 +