Semiconductor & Computer Engineering
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Difference between revisions of "intel/core i3/i3-9100t"
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== Cache == | == Cache == | ||
| − | {{main|intel/microarchitectures/ | + | {{main|intel/microarchitectures/coffee_lake#Memory_Hierarchy|l1=Coffee Lake § Cache}} |
{{cache size | {{cache size | ||
|l1 cache=256 KiB | |l1 cache=256 KiB | ||
Revision as of 00:13, 3 February 2018
| Edit Values | |
| Core i3-9100T | |
| General Info | |
| Designer | Intel |
| Manufacturer | Intel |
| Model Number | i3-9100T |
| Market | Desktop |
| Shop | Amazon |
| General Specs | |
| Family | Core i3 |
| Series | i3-9000 |
| Locked | Yes |
| Microarchitecture | |
| ISA | x86-64 (x86) |
| Microarchitecture | Coffee Lake |
| Core Name | Coffee Lake R |
| Process | 14 nm |
| Technology | CMOS |
| Word Size | 64 bit |
| Cores | 4 |
| Threads | 8 |
| Max Memory | 64 GiB |
| Multiprocessing | |
| Max SMP | 1-Way (Uniprocessor) |
| Electrical | |
| TDP | 35 W |
Core i3-9100T is a planned 64-bit mid-range performance x86 desktop processor by Intel set to be introduced in late 2018. The i3-9100T is fabricated on Intel's enhanced 14nm++ process based on the Coffee Lake microarchitecture.
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Preliminary Data! Information presented in this article deal with a microprocessor or chip that was recently announced or leaked, thus missing information regarding its features and exact specification. Information may be incomplete and can change by final release. |
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Leaked Info! Some of the information presented in this article is solely based on leaks that were published online or obtained directly by WikiChip. It goes without saying that this information could change, be incomplete, wrong, or even made up. It's highly advised to wait for an official product announcement. |
Cache
- Main article: Coffee Lake § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Facts about "Core i3-9100T - Intel"
| core count | 4 + |
| core name | Coffee Lake R + |
| designer | Intel + |
| family | Core i3 + |
| full page name | intel/core i3/i3-9100t + |
| has locked clock multiplier | true + |
| instance of | microprocessor + |
| isa | x86-64 + |
| isa family | x86 + |
| l1$ size | 256 KiB (262,144 B, 0.25 MiB) + |
| l1d$ description | 8-way set associative + |
| l1d$ size | 128 KiB (131,072 B, 0.125 MiB) + |
| l1i$ description | 8-way set associative + |
| l1i$ size | 128 KiB (131,072 B, 0.125 MiB) + |
| l2$ description | 4-way set associative + |
| l2$ size | 1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) + |
| l3$ description | 16-way set associative + |
| l3$ size | 8 MiB (8,192 KiB, 8,388,608 B, 0.00781 GiB) + |
| ldate | 3000 + |
| manufacturer | Intel + |
| market segment | Desktop + |
| max cpu count | 1 + |
| max memory | 65,536 MiB (67,108,864 KiB, 68,719,476,736 B, 64 GiB, 0.0625 TiB) + |
| microarchitecture | Coffee Lake + |
| model number | i3-9100T + |
| name | Core i3-9100T + |
| process | 14 nm (0.014 μm, 1.4e-5 mm) + |
| series | i3-9000 + |
| smp max ways | 1 + |
| tdp | 35 W (35,000 mW, 0.0469 hp, 0.035 kW) + |
| technology | CMOS + |
| thread count | 8 + |
| word size | 64 bit (8 octets, 16 nibbles) + |