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Difference between revisions of "esperanto/microarchitectures/et-minion"
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'''ET-Minion''' is an energy-efficient [[RISC-V]] microarchitecture designed by [[Esperanto]]. ET-Minion is also sold as a licensable [[synthesizable]] [[IP core]].
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'''ET-Minion''' is an energy-efficient [[RISC-V]] microarchitecture designed by [[Esperanto]]. ET-Minion is also sold as a licensable [[IP core]].
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== Process Technology ==
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ET-Minion is designed and optimized for [[TSMC]]'s [[7 nm process]] although it may be back-ported to older nodes in the future.
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== Architecture ==
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{{empty section}}

Revision as of 20:53, 25 December 2017

Edit Values
ET-Minion µarch
General Info
Arch TypeCPU
DesignerEsperanto
ManufacturerTSMC
Introduction2018
Process7 nm
Pipeline
TypeSuperscalar, Pipelined
OoOENo
SpeculativeYes
Reg RenamingNo
Instructions
ISARV64
ExtensionsI, M, A, F, D, C
Contemporary
ET-Maxion

ET-Minion is an energy-efficient RISC-V microarchitecture designed by Esperanto. ET-Minion is also sold as a licensable IP core.

Process Technology

ET-Minion is designed and optimized for TSMC's 7 nm process although it may be back-ported to older nodes in the future.

Architecture

New text document.svg This section is empty; you can help add the missing info by editing this page.
codenameET-Minion +
designerEsperanto +
first launched2018 +
full page nameesperanto/microarchitectures/et-minion +
instance ofmicroarchitecture +
instruction set architectureRV64 +
manufacturerTSMC +
microarchitecture typeCPU +
nameET-Minion +
process7 nm (0.007 μm, 7.0e-6 mm) +