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Difference between revisions of "amd/microarchitectures/k9"
< amd | microarchitectures
| Line 8: | Line 8: | ||
| phase-out = | | phase-out = | ||
| process = 65 nm | | process = 65 nm | ||
| + | |isa=x86-64 | ||
| succession = Yes | | succession = Yes | ||
Revision as of 18:59, 30 November 2017
| Edit Values | |
| K9 µarch | |
| General Info | |
| Arch Type | CPU |
| Designer | AMD |
| Manufacturer | AMD |
| Process | 65 nm |
| Instructions | |
| ISA | x86-64 |
| Succession | |
K9 was a planned microarchitecture developed by AMD as a successor to K8. AMD intended to bring massive parallelism to K9. The microarchitecture was reportedly scrapped after 6 months worth of work. The intended features and the exact reasons AMD cancelled K9 remain unknown.
Facts about "K9 - Microarchitectures - AMD"
| codename | K9 + |
| designer | AMD + |
| full page name | amd/microarchitectures/k9 + |
| instance of | microarchitecture + |
| instruction set architecture | x86-64 + |
| manufacturer | AMD + |
| microarchitecture type | CPU + |
| name | K9 + |
| process | 65 nm (0.065 μm, 6.5e-5 mm) + |