Semiconductor & Computer Engineering
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Difference between revisions of "intel/core i3/i3-9100"
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|technology=CMOS | |technology=CMOS | ||
|word size=64 bit | |word size=64 bit | ||
| + | |core count=4 | ||
| + | |thread count=8 | ||
|max cpus=1 | |max cpus=1 | ||
| + | |max memory=64 GiB | ||
}} | }} | ||
'''Core i3-9100''' is a planned {{arch|64}} mid-range performance [[x86]] desktop processor by [[Intel]] set to be introduced in [[2018]]. The i3-9100 is fabricated on Intel's 2nd generation [[10 nm process|10nm+ process]] based on the {{intel|Ice Lake|l=arch}} microarchitecture. | '''Core i3-9100''' is a planned {{arch|64}} mid-range performance [[x86]] desktop processor by [[Intel]] set to be introduced in [[2018]]. The i3-9100 is fabricated on Intel's 2nd generation [[10 nm process|10nm+ process]] based on the {{intel|Ice Lake|l=arch}} microarchitecture. | ||
Revision as of 11:32, 26 November 2017
Template:mpu Core i3-9100 is a planned 64-bit mid-range performance x86 desktop processor by Intel set to be introduced in 2018. The i3-9100 is fabricated on Intel's 2nd generation 10nm+ process based on the Ice Lake microarchitecture.
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Preliminary Data! Information presented in this article deal with a microprocessor or chip that was recently announced or leaked, thus missing information regarding its features and exact specification. Information may be incomplete and can change by final release. |
Facts about "Core i3-9100 - Intel"
| l1$ size | 256 KiB (262,144 B, 0.25 MiB) + |
| l1d$ description | 8-way set associative + |
| l1d$ size | 128 KiB (131,072 B, 0.125 MiB) + |
| l1i$ description | 8-way set associative + |
| l1i$ size | 128 KiB (131,072 B, 0.125 MiB) + |
| l2$ description | 4-way set associative + |
| l2$ size | 1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) + |
| l3$ description | 16-way set associative + |
| l3$ size | 8 MiB (8,192 KiB, 8,388,608 B, 0.00781 GiB) + |