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Difference between revisions of "hisilicon/k3/k3v2e"
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'''K3V2E''' is a {{arch|32}} [[quad-core]] mobile [[ARM]] microprocessor introduced by [[HiSilicon]] in late [[2012]]. This chip, which is fabricated on a [[40 nm process]], incorporates four {{armh|Cortex-A9|l=arch}} cores operating at 1.5 GHz. The K3V2 integrated [[Vivante]]'s {{vivante|GC4000}} (16 cores) [[IGP]] and supports up to 2 channels of LPDDR2-900 memory. The K3V2E is an enhanced version of the {{\\|K3V2}}, although the exact changes are not well-documented.
 
'''K3V2E''' is a {{arch|32}} [[quad-core]] mobile [[ARM]] microprocessor introduced by [[HiSilicon]] in late [[2012]]. This chip, which is fabricated on a [[40 nm process]], incorporates four {{armh|Cortex-A9|l=arch}} cores operating at 1.5 GHz. The K3V2 integrated [[Vivante]]'s {{vivante|GC4000}} (16 cores) [[IGP]] and supports up to 2 channels of LPDDR2-900 memory. The K3V2E is an enhanced version of the {{\\|K3V2}}, although the exact changes are not well-documented.
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== Cache ==
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{{main|arm holdings/microarchitectures/cortex-a9#Memory_Hierarchy|l1=Cortex-A9 § Cache}}
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{{cache size
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|l1 cache=256 KiB
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|l1i cache=128 KiB
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|l1i break=4x32 KiB
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|l1i desc=4-way set associative
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|l1d cache=128 KiB
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|l1d break=4x32 KiB
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|l1d desc=4-way set associative
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|l2 cache=1 MiB
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|l2 break=1x1 MiB
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|l2 desc=8-way set associative
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}}
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== Memory controller ==
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{{memory controller
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|type=LPDDR2-900
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|ecc=No
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|controllers=1
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|channels=2
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|width=32 bit
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|max bandwidth=6.71 GiB/s
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|bandwidth schan=3.35 GiB/s
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|bandwidth dchan=6.71 GiB/s
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}}
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== Graphics ==
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{{integrated graphics
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| gpu                = GC4000
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| designer            = Vivante
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| execution units    = 16
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| max displays        = 1
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| frequency          = 480 MHz
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| output crt          =
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| output sdvo        =
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| output dsi          = Yes
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| output edp          =
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| output dp          =
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| output hdmi        =
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| output vga          =
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| output dvi          =
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| directx ver        = 11
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| opengl es ver      = 3.1
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| openvg ver        = 1.1
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| opencl ver        = 1.2
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| opengl ver        = 3.0
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| max res dsi        = 1920x1200
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| max res dsi freq  =
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}}
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== Expansions ==
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* 4x high-speed UART interfaces
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* 2x SPI
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* 2x I2C + 2x I2C for camera
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* USB 2.0 On-The-Go (HS OTG) PHY
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* USB 1.1
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* 2x MMC/SD/SDIO interface
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* 22x GPIOs
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* 10 Timers
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== Block Diagram ==
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[[File:hisilicon k3v2 block.png|700px]]
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== Utilizing devices ==
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* [[used by::Huawei HN3-U01]]
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* [[used by::Huawei Ascend P6]] (P6-C00)
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* [[used by::Ascend W2]] (W2‐T00)
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* [[used by::Huawei Honor 3]]
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{{expand list}}

Revision as of 11:42, 6 September 2017

Template:mpu K3V2E is a 32-bit quad-core mobile ARM microprocessor introduced by HiSilicon in late 2012. This chip, which is fabricated on a 40 nm process, incorporates four Cortex-A9 cores operating at 1.5 GHz. The K3V2 integrated Vivante's GC4000 (16 cores) IGP and supports up to 2 channels of LPDDR2-900 memory. The K3V2E is an enhanced version of the K3V2, although the exact changes are not well-documented.


Cache

Main article: Cortex-A9 § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$256 KiB
262,144 B
0.25 MiB
L1I$128 KiB
131,072 B
0.125 MiB
4x32 KiB4-way set associative 
L1D$128 KiB
131,072 B
0.125 MiB
4x32 KiB4-way set associative 
L2$1 MiB
1,024 KiB
1,048,576 B
9.765625e-4 GiB
  1x1 MiB8-way set associative 

Memory controller

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeLPDDR2-900
Supports ECCNo
Controllers1
Channels2
Width32 bit
Max Bandwidth6.71 GiB/s
6,871.04 MiB/s
7.205 GB/s
7,204.808 MB/s
0.00655 TiB/s
0.0072 TB/s
Bandwidth
Single 3.35 GiB/s
Double 6.71 GiB/s

Graphics

[Edit/Modify IGP Info]

screen icon.svg
Integrated Graphics Information
GPUGC4000
DesignerVivante
Execution Units16Max Displays1
Frequency480 MHz
0.48 GHz
480,000 KHz
OutputDSI
Max Resolution
DSI1920x1200
Standards
DirectX11
OpenGL3.0
OpenCL1.2
OpenGL ES3.1
OpenVG1.1

Expansions

  • 4x high-speed UART interfaces
  • 2x SPI
  • 2x I2C + 2x I2C for camera
  • USB 2.0 On-The-Go (HS OTG) PHY
  • USB 1.1
  • 2x MMC/SD/SDIO interface
  • 22x GPIOs
  • 10 Timers

Block Diagram

hisilicon k3v2 block.png

Utilizing devices

  • Huawei HN3-U01
  • Huawei Ascend P6 (P6-C00)
  • Ascend W2 (W2‐T00)
  • Huawei Honor 3

This list is incomplete; you can help by expanding it.

Retrieved from "https://en.wikichip.org/w/index.php?title=hisilicon/k3/k3v2e&oldid=63649"
Facts about "K3V2E - HiSilicon"
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has ecc memory supportfalse +
integrated gpuGC4000 +
integrated gpu base frequency480 MHz (0.48 GHz, 480,000 KHz) +
integrated gpu designerVivante +
integrated gpu execution units16 +
l1$ size256 KiB (262,144 B, 0.25 MiB) +
l1d$ description4-way set associative +
l1d$ size128 KiB (131,072 B, 0.125 MiB) +
l1i$ description4-way set associative +
l1i$ size128 KiB (131,072 B, 0.125 MiB) +
l2$ description8-way set associative +
l2$ size1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) +
max memory bandwidth6.71 GiB/s (6,871.04 MiB/s, 7.205 GB/s, 7,204.808 MB/s, 0.00655 TiB/s, 0.0072 TB/s) +
max memory channels2 +
supported memory typeLPDDR2-900 +
used byHuawei HN3-U01 +, Huawei Ascend P6 +, Ascend W2 + and Huawei Honor 3 +