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Difference between revisions of "ibm/microarchitectures/z14"
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== Die ==
 
== Die ==
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=== Single-chip module (SCM) ===
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IBM's z14 Single-Chip Module (SCM) consists of a multi-layer metal substrate module that includes either:
 +
 
 +
* 1x Processor Unit (PU)
 +
* 1x System Controller (SC)
 +
 
 +
=== Processor Unit (PU) Die ===
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* [[IBM]]'s developed (now GlobalFoundries) [[14 nm process|14HP Process]]
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** CMOS FinFET SOI
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** 17 Metal Layers
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* 25.3 x 27.5 mm die
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* 695.75 mm² die size
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* [[deca-core]]
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* 5.2 GHz (192 ps cycle time)
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:: [[File:z14 die floor plan.png|650px]]
 +
 
 +
=== System Controller (SC) Die ===
 +
* [[IBM]]'s developed (now GlobalFoundries) [[14 nm process|14HP Process]]
 +
** CMOS FinFET SOI
 +
** 17 Metal Layers
 +
* 25.3 x 27.5 mm die
 +
* 695.75 mm² die size
 +
* 7,100,000,000 transistors
 +
* + 2,100,000,000 cells of eDRAM (~2.1B xTors + 2.1B capacitors)
 +
** 672 MiB shared eDRAM L4 Cache
 +
 
 +
 
 +
:: [[File:ibm z14 sc floor plan.png|650px]]

Revision as of 18:08, 20 July 2017

Edit Values
z14 µarch
General Info
Arch TypeCPU
DesignerIBM
ManufacturerGlobalFoundries
IntroductionJuly 17, 2017
Process14 nm
Pipeline
TypeSuperscalar, Pipelined
Instructions
ISAz/Architecture
Succession

z14 was a z/Architecture-based microarchitecture designed by IBM and introduced in 2017 for their z14 processors and mainframes. The z14 microarchitecture replaced the z13.

Process Technology

z14-based microprocessors are manufactured on GlobalFoundries's 14 nm FinFET Silicon-On-Insulator (SOI).

Architecture

Key changes from z13

  • 14 nm process (from 22 nm)
  • Higher clock frequency (5.2 GHz from 5 GHz)
  • Higher scalability
    • Up to 170-way multiprocessing (from 141-way)
  • Core
    • Improved Operand Store Compare (OSC) prediction
    • Faster branch wakeup
    • Improved instruction delivery
  • Cache
    • New directory design
      • Power efficient
    • L1I$ increased to 128 KiB/core (from 96 KiB/core; 33% increase)
    • L2D$ increased to 4 MiB/core (from 2 MiB/core; 100% increase)
    • L3$ increased to 128 MiB/CP (from 64 MiB/CP; 100% increase)
    • New 672 MiB/drawer of shared L4
  • Central Processor Assist for Cryptographic Function (CPACF)
    • Dedicated co-processor for each core
    • Claims 6x faster encryption functions (vs. z13)
      • 4x Advanced Encryption Standard (AES) speedup
    • Support for True Random Number Generator
    • New support for SHA-3 standard
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Overview

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Die

Single-chip module (SCM)

IBM's z14 Single-Chip Module (SCM) consists of a multi-layer metal substrate module that includes either:

  • 1x Processor Unit (PU)
  • 1x System Controller (SC)

Processor Unit (PU) Die

  • IBM's developed (now GlobalFoundries) 14HP Process
    • CMOS FinFET SOI
    • 17 Metal Layers
  • 25.3 x 27.5 mm die
  • 695.75 mm² die size
  • deca-core
  • 5.2 GHz (192 ps cycle time)


z14 die floor plan.png

System Controller (SC) Die

  • IBM's developed (now GlobalFoundries) 14HP Process
    • CMOS FinFET SOI
    • 17 Metal Layers
  • 25.3 x 27.5 mm die
  • 695.75 mm² die size
  • 7,100,000,000 transistors
  • + 2,100,000,000 cells of eDRAM (~2.1B xTors + 2.1B capacitors)
    • 672 MiB shared eDRAM L4 Cache


ibm z14 sc floor plan.png
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Facts about "z14 - Microarchitectures - IBM"
RDF feed
codenamez14 +
designerIBM +
first launchedJuly 17, 2017 +
full page nameibm/microarchitectures/z14 +
instance ofmicroarchitecture +
instruction set architecturez/Architecture +
manufacturerGlobalFoundries +
microarchitecture typeCPU +
namez14 +
process14 nm (0.014 μm, 1.4e-5 mm) +