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Difference between revisions of "dec/microarchitectures/strongarm"
(Created page with "{{dec title|StrongARM|arch}} {{microarchitecture |atype=CPU |name=StrongARM |designer=DEC |designer 2=ARM Holdings |manufacturer=DEC }}") |
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| Line 6: | Line 6: | ||
|designer 2=ARM Holdings | |designer 2=ARM Holdings | ||
|manufacturer=DEC | |manufacturer=DEC | ||
| + | |introduction=February 5, 1996 | ||
| + | |process=0.35 µm | ||
| + | |cores=1 | ||
| + | |oooe=No | ||
| + | |speculative=No | ||
| + | |renaming=No | ||
| + | |stages=5 | ||
| + | |decode=1-way | ||
| + | |isa=ARMv4 | ||
| + | |l1i=16 KiB | ||
| + | |l1i per=core | ||
| + | |l1i desc=32-way set associative | ||
| + | |l1d=16 KiB | ||
| + | |l1d per=core | ||
| + | |l1d desc=32-way set associative | ||
| + | |successor=XScale | ||
| + | |successor link=intel/microarchitectures/xscale | ||
}} | }} | ||
Revision as of 14:25, 29 May 2017
| Edit Values | |
| StrongARM µarch | |
| General Info | |
| Arch Type | CPU |
| Designer | DEC, ARM Holdings |
| Manufacturer | DEC |
| Introduction | February 5, 1996 |
| Process | 0.35 µm |
| Core Configs | 1 |
| Pipeline | |
| OoOE | No |
| Speculative | No |
| Reg Renaming | No |
| Stages | 5 |
| Decode | 1-way |
| Instructions | |
| ISA | ARMv4 |
| Cache | |
| L1I Cache | 16 KiB/core 32-way set associative |
| L1D Cache | 16 KiB/core 32-way set associative |
| Succession | |
Facts about "StrongARM - Microarchitectures - DEC"
| codename | StrongARM + |
| core count | 1 + |
| designer | DEC + and ARM Holdings + |
| first launched | February 5, 1996 + |
| full page name | dec/microarchitectures/strongarm + |
| instance of | microarchitecture + |
| instruction set architecture | ARMv4 + |
| manufacturer | DEC + and Intel + |
| microarchitecture type | CPU + |
| name | StrongARM + |
| pipeline stages | 5 + |
| process | 350 nm (0.35 μm, 3.5e-4 mm) + |