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Difference between revisions of "dec/strongarm"
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{{dec title|StrongARM}} | {{dec title|StrongARM}} | ||
| + | {{ic family | ||
| + | | title = StrongARM | ||
| + | | image = DEC StrongARM.jpg | ||
| + | | caption = A SA-110S model | ||
| + | | developer = DEC | ||
| + | | developer 2 = ARM Holdings | ||
| + | | developer 3 = Intel | ||
| + | | manufacturer = DEC | ||
| + | | manufacturer 2 = Intel | ||
| + | | type = Microprocessors | ||
| + | | first announced = | ||
| + | | first launched = | ||
| + | | production start = | ||
| + | | production end = 2004 | ||
| + | | arch = 32-bit embedded ARM processors | ||
| + | | isa = ARMv4 | ||
| + | | isa 2 = | ||
| + | | microarch = StrongARM | ||
| + | | word = 32 bit | ||
| + | | proc = 0.35 μm | ||
| + | | proc 2 = 0.25 μm | ||
| + | | tech = CMOS | ||
| + | | clock min = | ||
| + | | clock max = | ||
| + | | package = MBGA-256 | ||
| + | | package 2 = | ||
| + | | package 3 = | ||
| + | | package 4 = | ||
| + | |||
| + | | succession = Yes | ||
| + | | predecessor = | ||
| + | | predecessor link = | ||
| + | | successor = XScale | ||
| + | | successor link = intel/xscale | ||
| + | }} | ||
'''StrongARM''' ('''SA''') was a family of {{arch|32}} performance [[ARM]] processors for the embedded market designed collaboratively by [[DEC]] and [[ARM Holdings|ARM]]. | '''StrongARM''' ('''SA''') was a family of {{arch|32}} performance [[ARM]] processors for the embedded market designed collaboratively by [[DEC]] and [[ARM Holdings|ARM]]. | ||
Latest revision as of 13:02, 29 May 2017
| StrongARM | |
| |
| A SA-110S model | |
| Developer | DEC, ARM Holdings, Intel |
| Manufacturer | DEC, Intel |
| Type | Microprocessors |
| Architecture | 32-bit embedded ARM processors |
| ISA | ARMv4 |
| µarch | StrongARM |
| Word size | 32 bit 4 octets
8 nibbles |
| Process | 0.35 μm 350 nm , 0.25 μm3.5e-4 mm 250 nm
2.5e-4 mm |
| Technology | CMOS |
| Package | MBGA-256 |
| Succession | |
| → | |
| XScale | |
StrongARM (SA) was a family of 32-bit performance ARM processors for the embedded market designed collaboratively by DEC and ARM.
Facts about "StrongARM - DEC"
| designer | DEC +, ARM Holdings + and Intel + |
| full page name | dec/strongarm + |
| instance of | microprocessor family + |
| instruction set architecture | ARMv4 + |
| main designer | DEC + |
| manufacturer | DEC + and Intel + |
| microarchitecture | StrongARM + |
| name | StrongARM + |
| package | MBGA-256 + |
| process | 350 nm (0.35 μm, 3.5e-4 mm) + and 250 nm (0.25 μm, 2.5e-4 mm) + |
| technology | CMOS + |
| word size | 32 bit (4 octets, 8 nibbles) + |