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Difference between revisions of "loongson/godson 2/2e"
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'''Godson-2E''' ('''龙芯2E''') is a {{arch|64}} [[MIPS]] performance processor developed by [[Institute of Computing Technology of the Chinese Academy of Sciences|ICT]] and later [[Loongson]] for desktop computers. Introduced in early [[2006]], the Godson-2E operates at up to 1 GHz consuming 7W. This chip was manufactured on [[STMicroelectronics]]' [[90 nm process]] and provides roughly three times the performance of {{\\|2C}}. This processor is known as [[China]]'s first processor to reach gigahertz frequency.
 
'''Godson-2E''' ('''龙芯2E''') is a {{arch|64}} [[MIPS]] performance processor developed by [[Institute of Computing Technology of the Chinese Academy of Sciences|ICT]] and later [[Loongson]] for desktop computers. Introduced in early [[2006]], the Godson-2E operates at up to 1 GHz consuming 7W. This chip was manufactured on [[STMicroelectronics]]' [[90 nm process]] and provides roughly three times the performance of {{\\|2C}}. This processor is known as [[China]]'s first processor to reach gigahertz frequency.
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== Cache ==
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{{main|loongson/microarchitectures/GS464#Memory_Hierarchy|l1=GS464 § Cache}}
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{{cache size
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|l1 cache=128 KiB
 +
|l1i cache=64 KiB
 +
|l1i break=1x64 KiB
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|l1i desc=4-way set associative
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|l1d cache=64 KiB
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|l1d break=1x64 KiB
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|l1d desc=4-way set associative
 +
|l1d policy=
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|l2 cache=1 MiB
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|l2 break=1x1 MiB
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|l2 desc=4-way set associative
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|l2 policy=
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}}
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== Memory controller ==
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{{memory controller
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|type=DDR-333
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|ecc=Yes
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|max mem=2 GiB
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|controllers=1
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|channels=1
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|max bandwidth=4.962 GiB/s
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|bandwidth schan=4.962 GiB/s
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}}

Revision as of 15:25, 19 March 2017

Template:mpu Godson-2E (龙芯2E) is a 64-bit MIPS performance processor developed by ICT and later Loongson for desktop computers. Introduced in early 2006, the Godson-2E operates at up to 1 GHz consuming 7W. This chip was manufactured on STMicroelectronics' 90 nm process and provides roughly three times the performance of 2C. This processor is known as China's first processor to reach gigahertz frequency.

Cache

Main article: GS464 § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$128 KiB
131,072 B
0.125 MiB
L1I$64 KiB
65,536 B
0.0625 MiB
1x64 KiB4-way set associative 
L1D$64 KiB
65,536 B
0.0625 MiB
1x64 KiB4-way set associative 
L2$1 MiB
1,024 KiB
1,048,576 B
9.765625e-4 GiB
  1x1 MiB4-way set associative 

Memory controller

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR-333
Supports ECCYes
Max Mem2 GiB
Controllers1
Channels1
Max Bandwidth4.962 GiB/s
5,081.088 MiB/s
5.328 GB/s
5,327.907 MB/s
0.00485 TiB/s
0.00533 TB/s
Bandwidth
Single 4.962 GiB/s
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has ecc memory supporttrue +
l1$ size128 KiB (131,072 B, 0.125 MiB) +
l1d$ description4-way set associative +
l1d$ size64 KiB (65,536 B, 0.0625 MiB) +
l1i$ description4-way set associative +
l1i$ size64 KiB (65,536 B, 0.0625 MiB) +
l2$ description4-way set associative +
l2$ size1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) +
max memory bandwidth4.962 GiB/s (5,081.088 MiB/s, 5.328 GB/s, 5,327.907 MB/s, 0.00485 TiB/s, 0.00533 TB/s) +
max memory channels1 +
supported memory typeDDR-333 +