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Difference between revisions of "intel/microarchitectures/tiger lake"
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== See also == | == See also == | ||
| − | * AMD {{amd|Zen | + | * AMD {{amd|Zen 2|l=arch}} |
Revision as of 15:10, 6 March 2017
| Edit Values | |
| Tigerlake µarch | |
| General Info | |
| Arch Type | CPU |
| Designer | Intel |
| Manufacturer | Intel |
| Introduction | 2019 |
| Process | 10 nm |
| Succession | |
Tigerlake is a planned microarchitecture by Intel as a successor to Icelake. Tigerlake is expected to be fabricated using a 10 nm process. Tigerlake is the "Optimization" microarchitecture as part of Intel's PAO model.
Process Technology
- Main article: Cannonlake § Process Technology
Tigerlake is set to use the same 10 nm process that was designed for Cannonlake.
See also
- AMD Zen 2
Facts about "Tiger Lake - Microarchitectures - Intel"
| codename | Tiger Lake + |
| core count | 2 +, 4 +, 6 + and 8 + |
| designer | Intel + |
| first launched | September 2, 2020 + |
| full page name | intel/microarchitectures/tiger lake + |
| instance of | microarchitecture + |
| instruction set architecture | x86-64 + |
| manufacturer | Intel + |
| microarchitecture type | CPU + |
| name | Tiger Lake + |
| pipeline stages (max) | 19 + |
| pipeline stages (min) | 14 + |
| process | 10 nm (0.01 μm, 1.0e-5 mm) + |