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Difference between revisions of "ibm/microarchitectures/power9"
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== Die Shot == | == Die Shot == | ||
| − | + | === [[Tetracosa-Core]] === | |
| + | * GlobalFoundries [[14 nm process|14 nm FinFET Process]] | ||
| + | * 17-layer metal stack | ||
| + | * 8,000,000,000 transistors | ||
| + | |||
| + | [[File:power9 die shot.jpg|800px]] | ||
| + | |||
| + | [[File:power9 die shot (annotated).png|800px]] | ||
| + | |||
== See also == | == See also == | ||
* [[Intel]]'s {{intel|Skylake|l=arch}} & {{intel|Kaby Lake|l=arch}} | * [[Intel]]'s {{intel|Skylake|l=arch}} & {{intel|Kaby Lake|l=arch}} | ||
* [[AMD]]'s {{amd|Zen|l=arch}} | * [[AMD]]'s {{amd|Zen|l=arch}} | ||
* [[Qualcomm]]'s {{qualcomm|Falkor|l=arch}} | * [[Qualcomm]]'s {{qualcomm|Falkor|l=arch}} | ||
Revision as of 01:33, 1 February 2017
| Edit Values | |
| POWER9 µarch | |
| General Info | |
| Arch Type | CPU |
| Designer | IBM |
| Manufacturer | GlobalFoundries |
| Introduction | August, 2017 |
| Phase-out | August, 2018 |
| Process | 14 nm |
| Pipeline | |
| Type | Superscalar |
| Speculative | Yes |
| Reg Renaming | Yes |
| Stages | 12-16 |
| Instructions | |
| ISA | Power ISA v3.0 |
| Cache | |
| L1I Cache | 32 KiB/core |
| L1D Cache | 32 KiB/core |
| L2 Cache | 512 KiB/core |
| L3 Cache | 120 MiB/chip |
| Succession | |
POWER9 is the 14 nm microarchitecture for IBM's family of POWER9 processors set to be introduced in the 2nd half of 2017. POWER9 is a successor to the POWER8 microarchitecture.
Contents
Process Technology
POWER9 is set to be fabricated on GlobalFoundries' 14 nm FinFET process, the same process that's used by AMD for their Zen microarchitecture.
Compatibility
Initial support for POWER9 started with Linux Kernel 4.8.
| Vendor | OS | Version | Notes |
|---|---|---|---|
| IBM | AIX | 7.? | Support |
| IBM i | ? | Support | |
| Linux | Linux | Kernel 4.8 | Initial Support |
| Wind River | VxWorks | VxWorks 7.? | Support |
Compiler support
| Compiler | CPU | Arch-Favorable |
|---|---|---|
| GCC | -mcpu=pwr9 |
-mtune=pwr9
|
| LLVM | -mcpu=pwr9 |
-mtune=pwr9
|
| XL C/C++ | -mcpu=pwr9 |
-mtune=pwr9
|
Architecture
Key changes from POWER8
- 14 nm process (from 22 nm)
- 17-layer metal stack
- 8,000,000,000 transistors
- Support for Power ISA v3.0
- Higher single-thread performance
- New highly modular architecture
- Shorter pipeline
- 5 stages eliminated from fetch to compute vs POWER8
- Cache
- 120 MiB NUCA L3
- eDRAM
- 7 TB/s on-chip bandwidth
- 120 MiB NUCA L3
- Hardware Acceleration
- I/O Subsystem
- Virtualization
- QoS assistance
- New Interrupt architecture
- Workload-optimized frequency
- Hardware enforced trusted execution
Pipeline
 |
This section is empty; you can help add the missing info by editing this page. |
Die Shot
Tetracosa-Core
- GlobalFoundries 14 nm FinFET Process
- 17-layer metal stack
- 8,000,000,000 transistors
.png){kind=link}
See also
Facts about "POWER9 - Microarchitectures - IBM"
| codename | POWER9 + |
| designer | IBM + |
| first launched | August 2017 + |
| full page name | ibm/microarchitectures/power9 + |
| instance of | microarchitecture + |
| instruction set architecture | Power ISA v3.0 + |
| manufacturer | GlobalFoundries + |
| microarchitecture type | CPU + |
| name | POWER9 + |
| phase-out | August 2018 + |
| pipeline stages (max) | 16 + |
| pipeline stages (min) | 12 + |
| process | 14 nm (0.014 μm, 1.4e-5 mm) + |