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Difference between revisions of "intel/microarchitectures/tiger lake"
< intel | microarchitectures
| Line 1: | Line 1: | ||
{{intel title|Tigerlake|arch}} | {{intel title|Tigerlake|arch}} | ||
{{microarchitecture | {{microarchitecture | ||
| + | | atype = CPU | ||
| name = Tigerlake | | name = Tigerlake | ||
| designer = Intel | | designer = Intel | ||
Revision as of 18:20, 21 January 2017
| Edit Values | |
| Tigerlake µarch | |
| General Info | |
| Arch Type | CPU |
| Designer | Intel |
| Manufacturer | Intel |
| Introduction | 2019 |
| Process | 10 nm |
| Succession | |
Tigerlake is a planned microarchitecture by Intel as a successor to Icelake. Tigerlake is expected to be fabricated using a 10 nm process. Tigerlake is the "Optimization" microarchitecture as part of Intel's PAO model.
Process Technology
- Main article: Cannonlake § Process Technology
Tigerlake is set to use the same 10 nm process that was designed for Cannonlake.