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Difference between revisions of "amd/athlon mp/amp1900dms3c"
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The '''Athlon MP 1900+''' (OPN ''AMP1900DMS3C'') based on the {{amd|Palomino|l=core}} core was a {{arch|32}} [[x86]] [[multiprocessor]] developed by [[AMD]] and introduced in late [[2001]] for the server and workstation market. This MPU operated at 1.6 GHz with a FSB transfer rate of 266 MT/s (x12 multiplier). This processor, which was based on the {{amd|K7|K7 microarchitecture|l=arch}}, was manufactured on a mature [[180 nm]] copper interconnect technology at AMD's Fab 30 in Dresden, Germany. | The '''Athlon MP 1900+''' (OPN ''AMP1900DMS3C'') based on the {{amd|Palomino|l=core}} core was a {{arch|32}} [[x86]] [[multiprocessor]] developed by [[AMD]] and introduced in late [[2001]] for the server and workstation market. This MPU operated at 1.6 GHz with a FSB transfer rate of 266 MT/s (x12 multiplier). This processor, which was based on the {{amd|K7|K7 microarchitecture|l=arch}}, was manufactured on a mature [[180 nm]] copper interconnect technology at AMD's Fab 30 in Dresden, Germany. | ||
+ | |||
+ | == Cache == | ||
+ | {{main|amd/microarchitectures/k7#Memory_Hierarchy|l1=K7 § Cache}} | ||
+ | {{cache info | ||
+ | |l1i cache=64 KiB | ||
+ | |l1i break=1x64 KiB | ||
+ | |l1i desc=2-way set associative | ||
+ | |l1i extra= | ||
+ | |l1d cache=64 KiB | ||
+ | |l1d break=1x64 KiB | ||
+ | |l1d desc=2-way set associative | ||
+ | |l1d extra= | ||
+ | |l2 cache=64 KiB | ||
+ | |l2 break=1x64 KiB | ||
+ | |l2 desc=16-way set associative | ||
+ | |l2 extra= | ||
+ | |l3 cache= | ||
+ | |l3 break= | ||
+ | |l3 desc= | ||
+ | |l3 extra= | ||
+ | }} |
Revision as of 00:30, 17 November 2016
Template:mpu The Athlon MP 1900+ (OPN AMP1900DMS3C) based on the Palomino core was a 32-bit x86 multiprocessor developed by AMD and introduced in late 2001 for the server and workstation market. This MPU operated at 1.6 GHz with a FSB transfer rate of 266 MT/s (x12 multiplier). This processor, which was based on the K7 microarchitecture, was manufactured on a mature 180 nm copper interconnect technology at AMD's Fab 30 in Dresden, Germany.
Cache
- Main article: K7 § Cache
Cache Info [Edit Values] | ||
L1I$ | 64 KiB 65,536 B 0.0625 MiB |
1x64 KiB 2-way set associative |
L1D$ | 64 KiB 65,536 B 0.0625 MiB |
1x64 KiB 2-way set associative |
L2$ | 64 KiB 0.0625 MiB 65,536 B 6.103516e-5 GiB |
1x64 KiB 16-way set associative |
Facts about "Athlon MP 1900+ - AMD"
l1d$ description | 2-way set associative + |
l1d$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
l1i$ description | 2-way set associative + |
l1i$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
l2$ description | 16-way set associative + |
l2$ size | 0.0625 MiB (64 KiB, 65,536 B, 6.103516e-5 GiB) + |