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Difference between revisions of "amd/athlon mp/ahx1200ams3c"
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'''Athlon MP 1200''' (OPN ''AHX1200AMS3C'') based on the {{amd|Palomino|l=core}} core was a {{arch|32}} [[x86]] [[multiprocessor]] developed by [[AMD]] and introduced in [[2001]] for the server and workstation market. The MP 1200 was AMD's first dual-socket microprocessor (along with the {{\\|AHX1000AMS3C|1000}}). This model operated at 1,200 MHz with a FSB transfer rate of 266 MT/s with a typical TDP of 49.1 W. This processor, which was based on the {{amd|K7|K7 microarchitecture|l=arch}}, was manufactured on a mature [[180 nm]] copper interconnect technology at AMD's Fab 30 in Dresden, Germany.
 
'''Athlon MP 1200''' (OPN ''AHX1200AMS3C'') based on the {{amd|Palomino|l=core}} core was a {{arch|32}} [[x86]] [[multiprocessor]] developed by [[AMD]] and introduced in [[2001]] for the server and workstation market. The MP 1200 was AMD's first dual-socket microprocessor (along with the {{\\|AHX1000AMS3C|1000}}). This model operated at 1,200 MHz with a FSB transfer rate of 266 MT/s with a typical TDP of 49.1 W. This processor, which was based on the {{amd|K7|K7 microarchitecture|l=arch}}, was manufactured on a mature [[180 nm]] copper interconnect technology at AMD's Fab 30 in Dresden, Germany.
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== Cache ==
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{{main|amd/microarchitectures/k7#Memory_Hierarchy|l1=K7 § Cache}}
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{{cache info
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|l1i cache=64 KiB
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|l1i break=1x64 KiB
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|l1i desc=2-way set associative
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|l1i extra=
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|l1d cache=64 KiB
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|l1d break=1x64 KiB
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|l1d desc=2-way set associative
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|l1d extra=
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|l2 cache=64 KiB
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|l2 break=1x64 KiB
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|l2 desc=16-way set associative
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|l2 extra=
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|l3 cache=
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|l3 break=
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|l3 desc=
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|l3 extra=
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}}

Revision as of 00:30, 17 November 2016

Template:mpu Athlon MP 1200 (OPN AHX1200AMS3C) based on the Palomino core was a 32-bit x86 multiprocessor developed by AMD and introduced in 2001 for the server and workstation market. The MP 1200 was AMD's first dual-socket microprocessor (along with the 1000). This model operated at 1,200 MHz with a FSB transfer rate of 266 MT/s with a typical TDP of 49.1 W. This processor, which was based on the K7 microarchitecture, was manufactured on a mature 180 nm copper interconnect technology at AMD's Fab 30 in Dresden, Germany.

Cache

Main article: K7 § Cache
Cache Info [Edit Values]
L1I$ 64 KiB
65,536 B
0.0625 MiB
1x64 KiB 2-way set associative
L1D$ 64 KiB
65,536 B
0.0625 MiB
1x64 KiB 2-way set associative
L2$ 64 KiB
0.0625 MiB
65,536 B
6.103516e-5 GiB
1x64 KiB 16-way set associative
Retrieved from "https://en.wikichip.org/w/index.php?title=amd/athlon_mp/ahx1200ams3c&oldid=27694"
Facts about "Athlon MP 1200 - AMD"
RDF feed
l1d$ description2-way set associative +
l1d$ size64 KiB (65,536 B, 0.0625 MiB) +
l1i$ description2-way set associative +
l1i$ size64 KiB (65,536 B, 0.0625 MiB) +
l2$ description16-way set associative +
l2$ size0.25 MiB (256 KiB, 262,144 B, 2.441406e-4 GiB) +