Semiconductor & Computer Engineering
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Difference between revisions of "amd/k6-2/k6-2-500ack"
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== Cache == | == Cache == | ||
{{main|amd/microarchitectures/k6-2#Memory_Hierarchy|l1=K6-2 § Cache}} | {{main|amd/microarchitectures/k6-2#Memory_Hierarchy|l1=K6-2 § Cache}} | ||
| − | [[L2$]] can be 512 | + | [[L2$]] can be 512 KiB to 1 MiB, depending on manufacturer and [[motherboard]] model. L2$ is off-chip. |
{{cache info | {{cache info | ||
| − | |l1i cache=32 | + | |l1i cache=32 KiB |
| − | |l1i break=1x32 | + | |l1i break=1x32 KiB |
|l1i desc=2-way set associative | |l1i desc=2-way set associative | ||
|l1i extra= | |l1i extra= | ||
| − | |l1d cache=32 | + | |l1d cache=32 KiB |
| − | |l1d break=1x32 | + | |l1d break=1x32 KiB |
|l1d desc=2-way set associative | |l1d desc=2-way set associative | ||
|l1d extra= | |l1d extra= | ||
Revision as of 23:32, 20 September 2016
Template:mpu K6-2/500ACK was a 32-bit x86 K6-2-based mobile microprocessor designed and manufactured in 1999 by AMD. Manufactured using a 0.25 µm process, this MPU operated at 500 MHz with a FSB operating at 100 MHz.
Contents
Cache
- Main article: K6-2 § Cache
L2$ can be 512 KiB to 1 MiB, depending on manufacturer and motherboard model. L2$ is off-chip.
| Cache Info [Edit Values] | ||
| L1I$ | 32 KiB 32,768 B 0.0313 MiB |
1x32 KiB 2-way set associative |
| L1D$ | 32 KiB 32,768 B 0.0313 MiB |
1x32 KiB 2-way set associative |
Graphics
This SoC has no integrated graphics processing unit.
Features
- Auto-power down state
- Stop clock state
Documents
DataSheet
- Mobile AMD-K6-2 Processor Data Sheet; Publication #21896 Revision E/0, May 2000
Facts about "K6-2/500ACK - AMD"
| base frequency | 499.99 MHz (0.5 GHz, 499,990 kHz) + |
| bus rate | 99.99 MT/s (0.1 GT/s, 99,990 kT/s) + |
| bus speed | 99.99 MHz (0.1 GHz, 99,990 kHz) + |
| bus type | FSB + |
| clock multiplier | 5 + |
| core count | 1 + |
| core family | 5 + |
| core model | 8 + |
| core name | Chomper Extended + |
| core stepping | 12 + |
| core voltage | 2 V (20 dV, 200 cV, 2,000 mV) + |
| core voltage tolerance | 0.1 V + |
| cpuid | 58C + |
| designer | AMD + |
| die area | 81 mm² (0.126 in², 0.81 cm², 81,000,000 µm²) + |
| family | K6-2 + |
| first announced | September 20, 1999 + |
| first launched | September 20, 1999 + |
| full page name | amd/k6-2/k6-2-500ack + |
| instance of | microprocessor + |
| io voltage | 3.368 V (33.675 dV, 336.75 cV, 3,367.5 mV) + |
| io voltage tolerance | 7% + |
| l1d$ description | 2-way set associative + |
| l1d$ size | 32 KiB (32,768 B, 0.0313 MiB) + |
| l1i$ description | 2-way set associative + |
| l1i$ size | 32 KiB (32,768 B, 0.0313 MiB) + |
| ldate | September 20, 1999 + |
| manufacturer | AMD + |
| market segment | Mobile + |
| max case temperature | 353.15 K (80 °C, 176 °F, 635.67 °R) + |
| max cpu count | 1 + |
| max memory | 4,096 MiB (4,194,304 KiB, 4,294,967,296 B, 4 GiB, 0.00391 TiB) + |
| max storage temperature | 423.15 K (150 °C, 302 °F, 761.67 °R) + |
| microarchitecture | K6-2 + |
| min case temperature | 273.15 K (0 °C, 32 °F, 491.67 °R) + |
| min storage temperature | 208.15 K (-65 °C, -85 °F, 374.67 °R) + |
| model number | K6-2/500ACK + |
| name | K6-2/500ACK + |
| part number | AMD-K6-2/500ACK + |
| platform | Super 7 + |
| process | 250 nm (0.25 μm, 2.5e-4 mm) + |
| series | K6-2 Mobile P + |
| smp max ways | 1 + |
| technology | CMOS + |
| thread count | 1 + |
| transistor count | 9,300,000 + |
| word size | 32 bit (4 octets, 8 nibbles) + |