From WikiChip
Difference between revisions of "intel/xeon"
(→Xeon Timeline: combined intro) |
(→Xeon Timeline: combined families) |
||
Line 59: | Line 59: | ||
| style="background-color: #e6f7ff;" | 1998 || style="background-color: #fff5cc;" | {{intel|Pentium II Xeon}} || style="background-color: #ffe6ff;" | [[250 nm]] || style="background-color: #b3ffb3;" | {{intel|P6}} || style="background-color: #ebebe0;" | [[Drake]] || style="background-color: #eeffcc;" | 1 | | style="background-color: #e6f7ff;" | 1998 || style="background-color: #fff5cc;" | {{intel|Pentium II Xeon}} || style="background-color: #ffe6ff;" | [[250 nm]] || style="background-color: #b3ffb3;" | {{intel|P6}} || style="background-color: #ebebe0;" | [[Drake]] || style="background-color: #eeffcc;" | 1 | ||
|- style="height: 25px;" | |- style="height: 25px;" | ||
− | | style="background-color: #e6f7ff;" rowspan="2" | 1999 || style="background-color: #fff5cc;" | {{intel|Pentium III Xeon}} || style="background-color: #ffe6ff;" | [[250 nm]] || style="background-color: #b3ffb3;" | {{intel|P6}} || style="background-color: #ebebe0;" | [[Tanner]] || style="background-color: #eeffcc;" | 1 | + | | style="background-color: #e6f7ff;" rowspan="2" | 1999 || style="background-color: #fff5cc;" rowspan="2" | {{intel|Pentium III Xeon}} || style="background-color: #ffe6ff;" | [[250 nm]] || style="background-color: #b3ffb3;" | {{intel|P6}} || style="background-color: #ebebe0;" | [[Tanner]] || style="background-color: #eeffcc;" | 1 |
|- style="height: 25px;" | |- style="height: 25px;" | ||
− | + | | style="background-color: #ffe6ff;" | [[180 nm]] || style="background-color: #b3ffb3;" | {{intel|P6}} || style="background-color: #ebebe0;" | [[Cascades]] || style="background-color: #eeffcc;" | 1 | |
|- style="height: 25px;" | |- style="height: 25px;" | ||
− | | style="background-color: #e6f7ff;" | 2001 || style="background-color: #fff5cc;" | {{intel|Xeon (2001)|Xeon}} || style="background-color: #ffe6ff;" | [[180 nm]] || style="background-color: #b3ffb3;" | {{intel|NetBurst}} || style="background-color: #ebebe0;" | [[Foster]] || style="background-color: #eeffcc;" | 1 | + | | style="background-color: #e6f7ff;" | 2001 || style="background-color: #fff5cc;" rowspan="29" | {{intel|Xeon (2001)|Xeon}} || style="background-color: #ffe6ff;" | [[180 nm]] || style="background-color: #b3ffb3;" | {{intel|NetBurst}} || style="background-color: #ebebe0;" | [[Foster]] || style="background-color: #eeffcc;" | 1 |
|- style="height: 25px;" | |- style="height: 25px;" | ||
− | | style="background-color: #e6f7ff;" | 2002 | + | | style="background-color: #e6f7ff;" | 2002 || style="background-color: #ffe6ff;" | [[130 nm]] || style="background-color: #b3ffb3;" | {{intel|NetBurst}} || style="background-color: #ebebe0;" | [[Prestonia]] || style="background-color: #eeffcc;" | 1 |
|- style="height: 25px;" | |- style="height: 25px;" | ||
− | | style="background-color: #e6f7ff;" | 2003 | + | | style="background-color: #e6f7ff;" | 2003 || style="background-color: #ffe6ff;" | [[130 nm]] || style="background-color: #b3ffb3;" | {{intel|NetBurst}} || style="background-color: #ebebe0;" | [[Gallatin]] || style="background-color: #eeffcc;" | 1 |
|- style="height: 25px;" | |- style="height: 25px;" | ||
− | | style="background-color: #e6f7ff;" | 2004 | + | | style="background-color: #e6f7ff;" | 2004 || style="background-color: #ffe6ff;" | [[90 nm]] || style="background-color: #b3ffb3;" | {{intel|NetBurst}} || style="background-color: #ebebe0;" | [[Nocona]] || style="background-color: #eeffcc;" | 1 |
|- style="height: 25px;" | |- style="height: 25px;" | ||
− | | style="background-color: #e6f7ff;" rowspan="4" | 2005 | + | | style="background-color: #e6f7ff;" rowspan="4" | 2005 || style="background-color: #ffe6ff;" | [[90 nm]] || style="background-color: #b3ffb3;" | {{intel|NetBurst}} || style="background-color: #ebebe0;" | [[Irwindale]] || style="background-color: #eeffcc;" | 1 |
|- style="height: 25px;" | |- style="height: 25px;" | ||
− | + | | style="background-color: #ffe6ff;" | [[90 nm]] || style="background-color: #b3ffb3;" | {{intel|NetBurst}} || style="background-color: #ebebe0;" | [[Paxville]] || style="background-color: #eeffcc;" | 2 | |
|- style="height: 25px;" | |- style="height: 25px;" | ||
− | + | | style="background-color: #ffe6ff;" | [[90 nm]] || style="background-color: #b3ffb3;" | {{intel|NetBurst}} || style="background-color: #ebebe0;" | [[Potomac]] || style="background-color: #eeffcc;" | 1 | |
|- style="height: 25px;" | |- style="height: 25px;" | ||
− | + | | style="background-color: #ffe6ff;" | [[90 nm]] || style="background-color: #b3ffb3;" | {{intel|NetBurst}} || style="background-color: #ebebe0;" | [[Cranford]] || style="background-color: #eeffcc;" | 1 | |
|- style="height: 25px;" | |- style="height: 25px;" | ||
− | | style="background-color: #e6f7ff;" rowspan="6" | 2006 | + | | style="background-color: #e6f7ff;" rowspan="6" | 2006 || style="background-color: #ffe6ff;" | [[65 nm]] || style="background-color: #b3ffb3;" | {{intel|NetBurst}} || style="background-color: #ebebe0;" | [[Dempsey]] || style="background-color: #eeffcc;" | 2 |
|- style="height: 25px;" | |- style="height: 25px;" | ||
− | + | | style="background-color: #ffe6ff;" | [[65 nm]] || style="background-color: #b3ffb3;" | {{intel|NetBurst}} || style="background-color: #ebebe0;" | [[Tulsa]] || style="background-color: #eeffcc;" | 2 | |
|- style="height: 25px;" | |- style="height: 25px;" | ||
− | + | | style="background-color: #ffe6ff;" | [[65 nm]] || style="background-color: #b3ffb3;" | {{intel|microarchitectures/Modified Pentium M|MPM}} || style="background-color: #ebebe0;" | [[Sossaman]] || style="background-color: #eeffcc;" | 2 | |
|- style="height: 25px;" | |- style="height: 25px;" | ||
− | + | | style="background-color: #ffe6ff;" | [[65 nm]] || style="background-color: #b3ffb3;" | {{intel|microarchitectures/core|Core}} || style="background-color: #ebebe0;" | [[Woodcrest]] || style="background-color: #eeffcc;" | 2 | |
|- style="height: 25px;" | |- style="height: 25px;" | ||
− | + | | style="background-color: #ffe6ff;" | [[65 nm]] || style="background-color: #b3ffb3;" | {{intel|microarchitectures/core|Core}} || style="background-color: #ebebe0;" | [[Conroe]] || style="background-color: #eeffcc;" | 2 | |
|- style="height: 25px;" | |- style="height: 25px;" | ||
− | + | | style="background-color: #ffe6ff;" | [[65 nm]] || style="background-color: #b3ffb3;" | {{intel|microarchitectures/core|Core}} || style="background-color: #ebebe0;" | [[Clovertown]] || style="background-color: #eeffcc;" | 4 | |
|- style="height: 25px;" | |- style="height: 25px;" | ||
− | | style="background-color: #e6f7ff;" rowspan="5" | 2007 | + | | style="background-color: #e6f7ff;" rowspan="5" | 2007 || style="background-color: #ffe6ff;" | [[65 nm]] || style="background-color: #b3ffb3;" | {{intel|microarchitectures/core|Core}} || style="background-color: #ebebe0;" | [[Allendale]] || style="background-color: #eeffcc;" | 2 |
|- style="height: 25px;" | |- style="height: 25px;" | ||
− | + | | style="background-color: #ffe6ff;" | [[65 nm]] || style="background-color: #b3ffb3;" | {{intel|microarchitectures/core|Core}} || style="background-color: #ebebe0;" | [[Kentsfield]] || style="background-color: #eeffcc;" | 4 | |
|- style="height: 25px;" | |- style="height: 25px;" | ||
− | + | | style="background-color: #ffe6ff;" | [[65 nm]] || style="background-color: #b3ffb3;" | {{intel|microarchitectures/core|Core}} || style="background-color: #ebebe0;" | [[Tigerton]] || style="background-color: #eeffcc;" | 2 | |
|- style="height: 25px;" | |- style="height: 25px;" | ||
− | + | | style="background-color: #ffe6ff;" | [[45 nm]] || style="background-color: #b3ffb3;" | {{intel|microarchitectures/penryn|Penryn}} || style="background-color: #ebebe0;" | [[Wolfdale]] || style="background-color: #eeffcc;" | 2 | |
|- style="height: 25px;" | |- style="height: 25px;" | ||
− | + | | style="background-color: #ffe6ff;" | [[45 nm]] || style="background-color: #b3ffb3;" | {{intel|microarchitectures/penryn|Penryn}} || style="background-color: #ebebe0;" | [[Harpertown]] || style="background-color: #eeffcc;" | 4 | |
|- style="height: 25px;" | |- style="height: 25px;" | ||
− | | style="background-color: #e6f7ff;" rowspan="2" | 2008 | + | | style="background-color: #e6f7ff;" rowspan="2" | 2008 || style="background-color: #ffe6ff;" | [[45 nm]] || style="background-color: #b3ffb3;" | {{intel|microarchitectures/penryn|Penryn}} || style="background-color: #ebebe0;" | [[Yorkfield]] || style="background-color: #eeffcc;" | 4 |
|- style="height: 25px;" | |- style="height: 25px;" | ||
− | + | | style="background-color: #ffe6ff;" | [[45 nm]] || style="background-color: #b3ffb3;" | {{intel|microarchitectures/penryn|Penryn}} || style="background-color: #ebebe0;" | [[Dunnington]] || style="background-color: #eeffcc;" | 4,6 | |
|- style="height: 25px;" | |- style="height: 25px;" | ||
− | | style="background-color: #e6f7ff;" rowspan="3" | 2009 | + | | style="background-color: #e6f7ff;" rowspan="3" | 2009 || style="background-color: #ffe6ff;" | [[45 nm]] || style="background-color: #b3ffb3;" | {{intel|microarchitectures/nehalem|Nehalem}} || style="background-color: #ebebe0;" | [[Lynnfield]] || style="background-color: #eeffcc;" | 4 |
|- style="height: 25px;" | |- style="height: 25px;" | ||
− | + | | style="background-color: #ffe6ff;" | [[45 nm]] || style="background-color: #b3ffb3;" | {{intel|microarchitectures/nehalem|Nehalem}} || style="background-color: #ebebe0;" | [[Bloomfield]] || style="background-color: #eeffcc;" | 2,4 | |
|- style="height: 25px;" | |- style="height: 25px;" | ||
− | + | | style="background-color: #ffe6ff;" | [[45 nm]] || style="background-color: #b3ffb3;" | {{intel|microarchitectures/nehalem|Nehalem}} || style="background-color: #ebebe0;" | [[Gainestown]] || style="background-color: #eeffcc;" | 2,4 | |
|- style="height: 25px;" | |- style="height: 25px;" | ||
− | | style="background-color: #e6f7ff;" rowspan="6"| 2010 | + | | style="background-color: #e6f7ff;" rowspan="6"| 2010 || style="background-color: #ffe6ff;" | [[45 nm]] || style="background-color: #b3ffb3;" | {{intel|microarchitectures/nehalem|Nehalem}} || style="background-color: #ebebe0;" | [[Jasper Forest]] || style="background-color: #eeffcc;" | 1,2,4 |
|- style="height: 25px;" | |- style="height: 25px;" | ||
− | + | | style="background-color: #ffe6ff;" | [[45 nm]] || style="background-color: #b3ffb3;" | {{intel|microarchitectures/nehalem|Nehalem}} || style="background-color: #ebebe0;" | [[Beckton]] || style="background-color: #eeffcc;" | 4,6,8 | |
|- style="height: 25px;" | |- style="height: 25px;" | ||
− | + | | style="background-color: #ffe6ff;" | [[32 nm]] || style="background-color: #b3ffb3;" | {{intel|microarchitectures/westmere|Westmere}} || style="background-color: #ebebe0;" | [[Clarkdale]] || style="background-color: #eeffcc;" | 2 | |
|- style="height: 25px;" | |- style="height: 25px;" | ||
− | + | | style="background-color: #ffe6ff;" | [[32 nm]] || style="background-color: #b3ffb3;" | {{intel|microarchitectures/westmere|Westmere}} || style="background-color: #ebebe0;" | [[Gulftown]] || style="background-color: #eeffcc;" | 6 | |
|- style="height: 25px;" | |- style="height: 25px;" | ||
− | + | | style="background-color: #ffe6ff;" | [[32 nm]] || style="background-color: #b3ffb3;" | {{intel|microarchitectures/westmere|Westmere}} || style="background-color: #ebebe0;" | [[Westmere EP]] || style="background-color: #eeffcc;" | 2,4,6 | |
|- style="height: 25px;" | |- style="height: 25px;" | ||
− | | style="background-color: #fff5cc;" | {{intel|Xeon | + | | style="background-color: #fff5cc;" rowspan="20" | {{intel|Xeon E3}}<br>{{intel|Xeon E5}}<br>{{intel|Xeon E7}} || style="background-color: #ffe6ff;" | [[32 nm]] || style="background-color: #b3ffb3;" | {{intel|microarchitectures/westmere|Westmere}} || style="background-color: #ebebe0;" | [[Westmere EX]] || style="background-color: #eeffcc;" | 6,8,10 |
|- style="height: 25px;" | |- style="height: 25px;" | ||
− | | style="background-color: #e6f7ff;" | 2011 | + | | style="background-color: #e6f7ff;" | 2011 || style="background-color: #ffe6ff;" | [[32 nm]] || style="background-color: #b3ffb3;" | {{intel|microarchitectures/sandy bridge|Sandy Bridge}} || style="background-color: #ebebe0;" | [[Sandy Bridge]] || style="background-color: #eeffcc;" | 2,4 |
|- style="height: 25px;" | |- style="height: 25px;" | ||
− | | style="background-color: #e6f7ff;" rowspan="4" | 2012 | + | | style="background-color: #e6f7ff;" rowspan="4" | 2012 || style="background-color: #ffe6ff;" | [[32 nm]] || style="background-color: #b3ffb3;" | {{intel|microarchitectures/sandy bridge|Sandy Bridge}} || style="background-color: #ebebe0;" | [[Gladden]] || style="background-color: #eeffcc;" | 4 |
|- style="height: 25px;" | |- style="height: 25px;" | ||
− | + | | style="background-color: #ffe6ff;" | [[32 nm]] || style="background-color: #b3ffb3;" | {{intel|microarchitectures/sandy bridge|Sandy Bridge}} || style="background-color: #ebebe0;" | [[Sandy Bridge EN]] || style="background-color: #eeffcc;" | 4,6,8 | |
|- style="height: 25px;" | |- style="height: 25px;" | ||
− | + | | style="background-color: #ffe6ff;" | [[32 nm]] || style="background-color: #b3ffb3;" | {{intel|microarchitectures/sandy bridge|Sandy Bridge}} || style="background-color: #ebebe0;" | [[Sandy Bridge EP]] || style="background-color: #eeffcc;" | 4,6,8 | |
|- style="height: 25px;" | |- style="height: 25px;" | ||
− | + | | style="background-color: #ffe6ff;" | [[22 nm]] || style="background-color: #b3ffb3;" | {{intel|microarchitectures/ivy bridge|Ivy Bridge}} || style="background-color: #ebebe0;" | [[Ivy Bridge]] || style="background-color: #eeffcc;" | 2,4 | |
|- style="height: 25px;" | |- style="height: 25px;" | ||
− | | style="background-color: #e6f7ff;" rowspan="3" | 2013 | + | | style="background-color: #e6f7ff;" rowspan="3" | 2013 || style="background-color: #ffe6ff;" | [[22 nm]] || style="background-color: #b3ffb3;" | {{intel|microarchitectures/ivy bridge|Ivy Bridge}} || style="background-color: #ebebe0;" | [[Gladden]] || style="background-color: #eeffcc;" | 4 |
|- style="height: 25px;" | |- style="height: 25px;" | ||
− | + | | style="background-color: #ffe6ff;" | [[22 nm]] || style="background-color: #b3ffb3;" | {{intel|microarchitectures/ivy bridge|Ivy Bridge}} || style="background-color: #ebebe0;" | [[Ivy Bridge EP]] || style="background-color: #eeffcc;" | 4,6,8,10,12 | |
|- style="height: 25px;" | |- style="height: 25px;" | ||
− | + | | style="background-color: #ffe6ff;" | [[22 nm]] || style="background-color: #b3ffb3;" | {{intel|microarchitectures/haswell|Haswell}} || style="background-color: #ebebe0;" | [[Haswell WS]] || style="background-color: #eeffcc;" | 2,4 | |
|- style="height: 25px;" | |- style="height: 25px;" | ||
− | | style="background-color: #e6f7ff;" rowspan="3" | 2014 | + | | style="background-color: #e6f7ff;" rowspan="3" | 2014 || style="background-color: #ffe6ff;" | [[22 nm]] || style="background-color: #b3ffb3;" | {{intel|microarchitectures/ivy bridge|Ivy Bridge}} || style="background-color: #ebebe0;" | [[Ivy Bridge EN]] || style="background-color: #eeffcc;" | 4,6,8,10 |
|- style="height: 25px;" | |- style="height: 25px;" | ||
− | + | | style="background-color: #ffe6ff;" | [[22 nm]] || style="background-color: #b3ffb3;" | {{intel|microarchitectures/ivy bridge|Ivy Bridge}} || style="background-color: #ebebe0;" | [[Ivy Bridge EX]] || style="background-color: #eeffcc;" | 12,15 | |
|- style="height: 25px;" | |- style="height: 25px;" | ||
− | + | | style="background-color: #ffe6ff;" | [[22 nm]] || style="background-color: #b3ffb3;" | {{intel|microarchitectures/haswell|Haswell}} || style="background-color: #ebebe0;" | [[Haswell EP]] || style="background-color: #eeffcc;" | 4,6,8,10,12,14 | |
|- style="height: 25px;" | |- style="height: 25px;" | ||
− | | style="background-color: #e6f7ff;" rowspan="5" | 2015 | + | | style="background-color: #e6f7ff;" rowspan="5" | 2015 || style="background-color: #ffe6ff;" | [[22 nm]] || style="background-color: #b3ffb3;" | {{intel|microarchitectures/haswell|Haswell}} || style="background-color: #ebebe0;" | [[Haswell EN]] || style="background-color: #eeffcc;" | 4,6,8,10 |
|- style="height: 25px;" | |- style="height: 25px;" | ||
− | + | | style="background-color: #ffe6ff;" | [[22 nm]] || style="background-color: #b3ffb3;" | {{intel|microarchitectures/haswell|Haswell}} || style="background-color: #ebebe0;" | [[Haswell EX]] || style="background-color: #eeffcc;" | 8,10,12,14,16,18 | |
|- style="height: 25px;" | |- style="height: 25px;" | ||
− | + | | style="background-color: #ffe6ff;" | [[14 nm]] || style="background-color: #b3ffb3;" | {{intel|microarchitectures/broadwell|Broadwell}} || style="background-color: #ebebe0;" | [[Broadwell DE]] || style="background-color: #eeffcc;" | 4,6,8,12,16 | |
|- style="height: 25px;" | |- style="height: 25px;" | ||
− | + | | style="background-color: #ffe6ff;" | [[14 nm]] || style="background-color: #b3ffb3;" | {{intel|microarchitectures/broadwell|Broadwell}} || style="background-color: #ebebe0;" | [[Broadwell H]] || style="background-color: #eeffcc;" | 4 | |
|- style="height: 25px;" | |- style="height: 25px;" | ||
− | + | | style="background-color: #ffe6ff;" | [[14 nm]] || style="background-color: #b3ffb3;" | {{intel|microarchitectures/skylake|Skylake}} || style="background-color: #ebebe0;" | [[Skylake DT]] || style="background-color: #eeffcc;" | 4 | |
|- style="height: 25px;" | |- style="height: 25px;" | ||
− | | style="background-color: #e6f7ff;" rowspan="3" | 2016 | + | | style="background-color: #e6f7ff;" rowspan="3" | 2016 || style="background-color: #ffe6ff;" | [[14 nm]] || style="background-color: #b3ffb3;" | {{intel|microarchitectures/broadwell|Broadwell}} || style="background-color: #ebebe0;" | [[Broadwell EP]] || style="background-color: #eeffcc;" | 4,6,8,01,12,14,16,18,20,22 |
|- style="height: 25px;" | |- style="height: 25px;" | ||
− | + | | style="background-color: #ffe6ff;" | [[14 nm]] || style="background-color: #b3ffb3;" | {{intel|microarchitectures/broadwell|Broadwell}} || style="background-color: #ebebe0;" | [[Broadwell EX]] || style="background-color: #eeffcc;" | 8,10,14,16,20,22,24 | |
|- style="height: 25px;" | |- style="height: 25px;" | ||
− | + | | style="background-color: #ffe6ff;" | [[14 nm]] || style="background-color: #b3ffb3;" | {{intel|microarchitectures/skylake|Skylake}} || style="background-color: #ebebe0;" | [[Skylake H]] || style="background-color: #eeffcc;" | 4 | |
|} | |} | ||
Revision as of 13:48, 13 September 2016
Xeon | |
Past and current logos | |
Developer | Intel |
Manufacturer | Intel |
Type | Microprocessors |
Introduction | June 29, 1998 (announced) 1998 (launch) |
Production | 1998 |
ISA | x86-64 |
µarch | P6, NetBurst, Core, Penryn, Nehalem, Westmere, Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake |
Word size | 32 bit 4 octets , 64 bit8 nibbles 8 octets
16 nibbles |
Process | 350 nm 0.35 μm , 250 nm3.5e-4 mm 0.25 μm , 180 nm2.5e-4 mm 0.18 μm , 65 nm1.8e-4 mm 0.065 μm , 45 nm6.5e-5 mm 0.045 μm , 32 nm4.5e-5 mm 0.032 μm , 22 nm3.2e-5 mm 0.022 μm , 14 nm2.2e-5 mm 0.014 μm
1.4e-5 mm |
Technology | CMOS |
Clock | 400 MHz-4000 MHz |
Succession | |
← | |
Pentium Pro |
Xeon (pronounced "Zee-On") is an extended family of high-performance x86 microprocessors developed by Intel for server environments and non-consumer workstations. Over the years Xeon has grown to focus on high-bandwidth, large-memory, and highly concurrent workloads. Xeon processors typically incorporate a large number of cores, large cache, and support for large amount of memory. Xeon offers models for both uniprocessor or multiprocessors.
Xeon Timeline
This article is still a stub and needs your attention. You can help improve this article by editing this page and adding the missing information. |
Facts about "Xeon - Intel"
designer | Intel + |
first announced | June 29, 1998 + |
first launched | 1998 + |
full page name | intel/xeon + |
instance of | microprocessor extended family + |
instruction set architecture | x86-64 + |
main designer | Intel + |
manufacturer | Intel + |
microarchitecture | P6 +, NetBurst +, Core +, Penryn +, Nehalem +, Westmere +, Sandy Bridge +, Ivy Bridge +, Haswell +, Broadwell + and Skylake + |
name | Xeon + |
process | 350 nm (0.35 μm, 3.5e-4 mm) +, 250 nm (0.25 μm, 2.5e-4 mm) +, 180 nm (0.18 μm, 1.8e-4 mm) +, 65 nm (0.065 μm, 6.5e-5 mm) +, 45 nm (0.045 μm, 4.5e-5 mm) +, 32 nm (0.032 μm, 3.2e-5 mm) +, 22 nm (0.022 μm, 2.2e-5 mm) + and 14 nm (0.014 μm, 1.4e-5 mm) + |
technology | CMOS + |
word size | 32 bit (4 octets, 8 nibbles) + and 64 bit (8 octets, 16 nibbles) + |