Semiconductor & Computer Engineering
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PipeRench is designed as a reconfigurable fabric. The chip breaks down each of its pipeline stages into individual ''stripes''. Each strip has a set of simple execution units (EU/PE), register files, and a interconnection network. By configuring each of the stripes using the interconnect network, it's possible to virtualize different kind of custom hardware. The ALU, for example contains additional circuitry to facilitate [[bit-slice microprocessor|bit-slicing]]. | PipeRench is designed as a reconfigurable fabric. The chip breaks down each of its pipeline stages into individual ''stripes''. Each strip has a set of simple execution units (EU/PE), register files, and a interconnection network. By configuring each of the stripes using the interconnect network, it's possible to virtualize different kind of custom hardware. The ALU, for example contains additional circuitry to facilitate [[bit-slice microprocessor|bit-slicing]]. | ||
| + | {{expand section}} | ||
== Die Shot == | == Die Shot == | ||
[[File:cmu piperench die.jpg|450px]] | [[File:cmu piperench die.jpg|450px]] | ||
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| + | 49 mm² on a [[180 nm process]]. | ||
== Documents == | == Documents == | ||
Revision as of 10:34, 22 June 2016
Template:mpu PipeRench was a research microprocessor designed at Carnegie Mellon University in the early 2000s. PipeRench was developed with a reconfigurable pipeline. This allows what would otherwise have to be implemented as specialized embedded chips to be implemented in a more generic way using PipeRench through reconfiguration.
Technology developed for this project was eventually leased to Rapport for their Kilocore architecture which eventually resulted in the KC256, a 256-core chip.
Architecture
PipeRench is designed as a reconfigurable fabric. The chip breaks down each of its pipeline stages into individual stripes. Each strip has a set of simple execution units (EU/PE), register files, and a interconnection network. By configuring each of the stripes using the interconnect network, it's possible to virtualize different kind of custom hardware. The ALU, for example contains additional circuitry to facilitate bit-slicing.
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This section requires expansion; you can help adding the missing info. |
Die Shot
49 mm² on a 180 nm process.
Documents
- Seth C. Goldstein, Herman Schmit, Mihai Budiu, Srihari Cadambi, Matt Moe, and R. Reed Taylor, "PipeRench: A Reconfigurable Architecture and Compiler", April 2000, Carnegie Mellon University Computer Science Department.
External links
| base frequency | 120 MHz (0.12 GHz, 120,000 kHz) + |
| bus speed | 60 MHz (0.06 GHz, 60,000 kHz) + |
| clock multiplier | 2 + |
| designer | Carnegie Mellon University + |
| die area | 49 mm² (0.076 in², 0.49 cm², 49,000,000 µm²) + |
| first announced | April 2000 + |
| first launched | 2002 + |
| full page name | cmu/piperench + |
| instance of | microprocessor + |
| ldate | 2002 + |
| main image |  + |
| main image caption | Logo + |
| name | PipeRench + |
| power dissipation | 4 W (4,000 mW, 0.00536 hp, 0.004 kW) + |
| process | 180 nm (0.18 μm, 1.8e-4 mm) + |
| technology | CMOS + |
| transistor count | 3,650,000 + |
