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Difference between revisions of "intel/microarchitectures/tiger lake"
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{{microarchitecture | {{microarchitecture | ||
| name = Tigerlake | | name = Tigerlake | ||
| + | | designer = Intel | ||
| manufacturer = Intel | | manufacturer = Intel | ||
| introduction = 2019-2020 | | introduction = 2019-2020 | ||
Revision as of 18:14, 16 May 2016
| Edit Values | |
| Tigerlake µarch | |
| General Info |
Tigerlake is a planned microarchitecture by Intel as a successor to Icelake. Tigerlake is expected to be fabricated using a 7 nm or 10 nm process.
Facts about "Tiger Lake - Microarchitectures - Intel"
| codename | Tiger Lake + |
| core count | 2 +, 4 +, 6 + and 8 + |
| designer | Intel + |
| first launched | September 2, 2020 + |
| full page name | intel/microarchitectures/tiger lake + |
| instance of | microarchitecture + |
| instruction set architecture | x86-64 + |
| manufacturer | Intel + |
| microarchitecture type | CPU + |
| name | Tiger Lake + |
| pipeline stages (max) | 19 + |
| pipeline stages (min) | 14 + |
| process | 10 nm (0.01 μm, 1.0e-5 mm) + |