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Difference between revisions of "intel/roadmap"
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* Sierra Forest (2024) • Crestmont (E) SP • SRF-SP | * Sierra Forest (2024) • Crestmont (E) SP • SRF-SP | ||
* Clearwater Forest (2025) • CWF-AP (LGA7529) • Darkmont (E) • 18A • CWF-SP (LGA4710) | * Clearwater Forest (2025) • CWF-AP (LGA7529) • Darkmont (E) • 18A • CWF-SP (LGA4710) | ||
| − | * Nova Lake (2026) • Coyote Cove (P), Arctic Wolf (E) • NVL-S/H | + | * Nova Lake (2026) • Coyote Cove (P), Arctic Wolf (E) • NVL-S/H • Core Ultra 400 (LGA1954) • Royal Core 1.0 P-Core |
* Razer Lake (2027) • Griffin Cove (P), Golden Eagle (E) • RZL-M/H | * Razer Lake (2027) • Griffin Cove (P), Golden Eagle (E) • RZL-M/H | ||
* Beast Lake (2026/2027) • Successor to Arrow Lake • Royal Core 1.1 P-Core | * Beast Lake (2026/2027) • Successor to Arrow Lake • Royal Core 1.1 P-Core | ||
| − | * Titan Lake (2027) • ? --> | + | * Titan Lake (2027) • ? |
| + | * Serpent Lake (2028) • ? New P-Core "Cobra Core," could also be "Cobra Cove" to follow Intel's naming scheme | ||
| + | --> | ||
* [[Core|Intel Core]] (P) • ''[[Intel Atom]]'' (E) | * [[Core|Intel Core]] (P) • ''[[Intel Atom]]'' (E) | ||
| Line 25: | Line 27: | ||
|- | |- | ||
! colspan="2" | Date || Fab || Mobile L || Mobile H || Desktop L || Desktop H || Workstation L || Workstation H || Server 2P || Server 4P | ! colspan="2" | Date || Fab || Mobile L || Mobile H || Desktop L || Desktop H || Workstation L || Workstation H || Server 2P || Server 4P | ||
| + | |- | ||
| + | | rowspan="4" | <div style="transform:rotate(-90deg);">'''2028'''</div> || style="transform:rotate(-90deg)" | '''Q4''' || rowspan="4" | <div style="transform:rotate(-90deg);">[[14A]]</div> || {{tblnk}} || {{tblnk}} || {{tblnk}} || style="background-color: #ffe6ff;" | {{intel|Future Lake|l=arch}} S | ||
| + | |- | ||
| + | | style="transform: rotate(-90deg);" | '''Q3''' | ||
| + | |- | ||
| + | | style="transform: rotate(-90deg);" | '''Q2''' || {{tblnk}} || {{tblnk}} || {{tblnk}} || style="background-color: #ffe6ff;" | {{intel|Serpent Lake|l=arch}} S | ||
| + | |- | ||
| + | | style="transform: rotate(-90deg);" | '''Q1''' | ||
|- | |- | ||
| rowspan="4" | <div style="transform:rotate(-90deg);">'''2027'''</div> || style="transform:rotate(-90deg)" | '''Q4''' || rowspan="4" | <div style="transform:rotate(-90deg);">[[14A]]</div> || {{tblnk}} || {{tblnk}} || {{tblnk}} || style="background-color: #ffe6ff;" | {{intel|Titan Lake|l=arch}} S | | rowspan="4" | <div style="transform:rotate(-90deg);">'''2027'''</div> || style="transform:rotate(-90deg)" | '''Q4''' || rowspan="4" | <div style="transform:rotate(-90deg);">[[14A]]</div> || {{tblnk}} || {{tblnk}} || {{tblnk}} || style="background-color: #ffe6ff;" | {{intel|Titan Lake|l=arch}} S | ||
| Line 39: | Line 49: | ||
| style="transform: rotate(-90deg);" | '''Q3''' | | style="transform: rotate(-90deg);" | '''Q3''' | ||
|- | |- | ||
| − | | style="transform: rotate(-90deg);" | '''Q2''' || {{tblnk}} || {{tblnk}} || {{intel|Nova Lake HX|l=core}} | + | | style="transform: rotate(-90deg);" | '''Q2''' || {{tblnk}} || {{tblnk}} || {{intel|Nova Lake HX|l=core}} || {{tblnk}} || {{intel|Nova Lake AX|l=core}} |
|- | |- | ||
| style="transform: rotate(-90deg);" | '''Q1''' || {{tblnk}} || style="background-color: #fff5cc;" | {{intel|Nova Lake U|l=core}} || style="background-color: #ffe6ff;" | {{intel|Nova Lake H|l=core}} || style="background-color: #ffe6ff;" | {{intel|Nova Lake|l=arch}} S || style="background-color: #e6f7ff;" | {{intel|Nova Lake SK|l=core}} | | style="transform: rotate(-90deg);" | '''Q1''' || {{tblnk}} || style="background-color: #fff5cc;" | {{intel|Nova Lake U|l=core}} || style="background-color: #ffe6ff;" | {{intel|Nova Lake H|l=core}} || style="background-color: #ffe6ff;" | {{intel|Nova Lake|l=arch}} S || style="background-color: #e6f7ff;" | {{intel|Nova Lake SK|l=core}} | ||
| Line 74: | Line 84: | ||
| style="transform: rotate(-90deg);" | '''Q2''' || {{tblnk}} || style="background-color: #fff5cc;" | {{intel|Raptor Lake U|l=core}} || style="background-color: #ffe6ff;" | {{intel|Raptor Lake H|l=core}} || {{tblnk}} || {{tblnk}} || {{intel|Raptor Lake PX|l=core}} | | style="transform: rotate(-90deg);" | '''Q2''' || {{tblnk}} || style="background-color: #fff5cc;" | {{intel|Raptor Lake U|l=core}} || style="background-color: #ffe6ff;" | {{intel|Raptor Lake H|l=core}} || {{tblnk}} || {{tblnk}} || {{intel|Raptor Lake PX|l=core}} | ||
|- | |- | ||
| − | | style="transform: rotate(-90deg);" | '''Q1''' || {{tblnk}} || {{tblnk}} || {{tblnk}} || {{tblnk}} || style="background-color: #b3ffb3;" | ''{{intel|Twin Lake | + | | style="transform: rotate(-90deg);" | '''Q1''' || {{tblnk}} || {{tblnk}} || {{tblnk}} || {{tblnk}} || style="background-color: #b3ffb3;" | ''{{intel|Twin Lake|l=arch}}'' |
|- <!-- Alder Lake H, Alder Lake HX, Alder Lake U, Alder Lake M, Alder Lake S, Alder Lake P --> | |- <!-- Alder Lake H, Alder Lake HX, Alder Lake U, Alder Lake M, Alder Lake S, Alder Lake P --> | ||
| rowspan="4" | <div style="transform:rotate(-90deg);">'''2021'''</div> || style="transform:rotate(-90deg)" | '''Q4''' || rowspan="2" | <div style="transform:rotate(-90deg);">[[10 nm process|10 nm]]</div> || {{tblnk}} || {{intel|Alder Lake M|l=core}} || {{intel|Alder Lake HX|l=core}} || style="background-color: #ffe6ff;" | {{intel|Alder Lake S|l=core}} || style="background-color: #e6f7ff;" | {{intel|Alder Lake N|l=core}} || style="background-color: #e6f7ff;" | {{intel|Alder Lake P|l=core}} | | rowspan="4" | <div style="transform:rotate(-90deg);">'''2021'''</div> || style="transform:rotate(-90deg)" | '''Q4''' || rowspan="2" | <div style="transform:rotate(-90deg);">[[10 nm process|10 nm]]</div> || {{tblnk}} || {{intel|Alder Lake M|l=core}} || {{intel|Alder Lake HX|l=core}} || style="background-color: #ffe6ff;" | {{intel|Alder Lake S|l=core}} || style="background-color: #e6f7ff;" | {{intel|Alder Lake N|l=core}} || style="background-color: #e6f7ff;" | {{intel|Alder Lake P|l=core}} | ||
| Line 191: | Line 201: | ||
KF – Unlocked clock multiplier + No integrated graphics | KF – Unlocked clock multiplier + No integrated graphics | ||
KS – Unlocked clock multiplier + Special edition | KS – Unlocked clock multiplier + Special edition | ||
| + | ---- | ||
| + | >> Intel CPU Roadmap 2027-29: Razer Lake, Titan Lake & Serpent Lake with NVIDIA RTX iGPU | ||
| + | |||
| + | Intel & AMD Laptop CPU Families (Expected): | ||
| + | |||
| + | Segment 2022 2023 2024 2025 2026 2027 | ||
| + | |||
| + | Enthusiast Alder Lake-HX (Intel) Raptor Lake-HX (Intel) | ||
| + | Dragon Range (AMD) Raptor Lake Refresh-HX (Intel) Arrow Lake-HX (Intel) | ||
| + | Fire Range (AMD) | ||
| + | Strix Point Halo (AMD) Arrow Lake-HX Refresh (Intel) | ||
| + | Medusa Halo ? (AMD) Nova Lake-AX (Intel) | ||
| + | Nova Lake-HX (Intel) | ||
| + | Gator Range (AMD) | ||
| + | |||
| + | High-End Alder Lake-H (Intel) | ||
| + | Rembrandt (AMD) Raptor Lake-H (Intel) | ||
| + | Meteor Lake-H (Intel) | ||
| + | Phoenix (AMD) | ||
| + | Rembrandt-R (AMD) Meteor Lake-H (Intel) | ||
| + | Raptor Lake Refresh-H (Intel) | ||
| + | Arrow Lake-H (Intel) | ||
| + | Hawk Point (AMD) | ||
| + | Strix Point (AMD) Arrow Lake-H (Intel) | ||
| + | Krakan Point (AMD) | ||
| + | Gorgon Point (AMD) | ||
| + | Panther Lake-H (Intel) Arrow Lake-H Refresh (Intel) | ||
| + | Panther Lake-H (Intel) | ||
| + | Medusa Point (AMD) Nova Lake-H (Intel) | ||
| + | |||
| + | Mainstream Alder Lake-U (Intel) | ||
| + | Rembrandt (AMD) | ||
| + | Barcelo (AMD) | ||
| + | Raptor Lake-U (Intel) | ||
| + | Phoenix (AMD) | ||
| + | Rembrandt-R (AMD) Meteor Lake-U (Intel) | ||
| + | Raptor Lake Refresh-U (Intel) | ||
| + | Hawk Point (AMD) | ||
| + | Strix Point (AMD) Arrow Lake-U | ||
| + | Panther Lake-U (Intel) Panther Lake-U (Intel) | ||
| + | Medusa BB (AMD) Nova Lake-U (Intel) | ||
| + | |||
| + | Low-Power Alder Lake-U (Intel) | ||
| + | Mendocino (AMD) Raptor Lake-U (Intel) Meteor Lake-U (Intel) | ||
| + | Lunar Lake-M (Intel) Lunar Lake-M (Intel) Lunar Lake-M (Intel) TBD | ||
| + | ---- | ||
| + | Intel Beast Lake | ||
| + | Release Date: 2026 or 2027 # | ||
| + | Successor to Arrow Lake # | ||
| + | Uses Royal Core 1.1 P-Core architecture # | ||
| + | |||
| + | Intel Razer Lake | ||
| + | Release Date: Unknown # | ||
| + | Intel Core Ultra 400 Series # | ||
| + | |||
| + | Intel Nova Lake [updated] | ||
| + | Release Date: Q3 2026 # # | ||
| + | Engineering samples ready as of Feb 2025 # | ||
| + | Successor to Arrow Lake | ||
| + | Core Ultra 300 Series # | ||
| + | New P-Core "Coyote Cove" # | ||
| + | Other leak: 16 Coyote Cove P-Cores and 32 Arctic Wolf E-Cores and 4 LPE cores # | ||
| + | Also considering 28-core (8P + 16E + 4LPE), and 16-core (4P + 8E + 4LPE) SKUs # | ||
| + | Up to 52 cores # | ||
| + | ES: Running 52 cores at 4.8 GHz # | ||
| + | NVL-SK: 2x (8P+16E), NVL-HX: 1x (8P+16E), NVL-S/NVL-H: 4P+8E, NVL-U: 4P+OE # | ||
| + | Nova Lake AX: 8P, 16E, 4LPE, bigger iGPU with 384 EUs, LPDDR5X # | ||
| + | Nova Lake HX: BGA2540 # | ||
| + | Core Ultra 9: 16P, 32E, 4LP, 144 MB L3, 150 W # | ||
| + | Core Ultra 7: 14P, 24E, 4LP, 120 MB L3, 150 W # | ||
| + | Core Ultra 5 K and KF: 8P, 16E, 4LP, 72 MB L3, 125 W # | ||
| + | Core Ultra 5 non-K Med: 8P, 12E, 4LP, 33 MB L3, 125 W # | ||
| + | Core Ultra 5 non-K Value: 6P, 8E, 4LP, 24 MB L3, 65 W # | ||
| + | Core Ultra 3 Med: 4P, 8E, 4 P, 18 MB L3, 65 W # | ||
| + | Core Ultra 3 Entry: 4P, 4E, 4LP, 12 MB L3, 65 W # | ||
| + | Possibly 4-core variant for low power laptops # | ||
| + | Unlike Lunar Lake, no on-package memory # | ||
| + | Uses TSMC 2 nanometer process for the CPU tile # # | ||
| + | Should be "quite a jump from Arrow Lake (ARL) in terms of MT performance" # | ||
| + | Intel bLLC could be their X3D equivalent, offering bigger L3 cache for gaming performance # | ||
| + | Socket LGA1954 # | ||
| + | Older coolers are compatible # # | ||
| + | Also using Intel 14 A # | ||
| + | DDR5 memory # PCI Express 6.0 # | ||
| + | New Gen 6 NPU, newer than Panther Lake # | ||
| + | Adds support for AVX10 and APX # | ||
| + | Or might not have those instructions # | ||
| + | AVX10.2 mentioned, too # | ||
| + | Xe3P iGPU # | ||
| + | RT support not available on all iGPU models # | ||
| + | |||
| + | Intel Wildcat Lake | ||
| + | Release Date: 2025 # | ||
| + | Abbreviated WCL # | ||
| + | Successor to Alder Lake-N # | ||
| + | Targets lightweight laptops and mini-PCs # | ||
| + | Soldered BGA 1516 socket, 35x25 mm # | ||
| + | 18A process # | ||
| + | 2P + 4LPE configuration # | ||
| + | Cougar Cove P-Cores, Darkmont LPE cores # | ||
| + | Thunderbolt 4 # | ||
| + | LPDDR5X memory # | ||
| + | Leaked model: 2P+0E+4LP+2Xe3, 40 TOPS # | ||
| + | iGPU uses Xe3 Celestial architecture, 2 Xe cores with 32 EUs # | ||
| + | No ray tracing # | ||
| + | |||
| + | Intel Panther Lake [updated] | ||
| + | Release Date: H2 2025 # | ||
| + | Our in depth technical deep dive article of Panther Lake can be found here | ||
| + | Just one model in 2025, the others in 2026 # | ||
| + | Successor to "Lunar Lake" # | ||
| + | Actual processor first displayed in Oct 2024 # | ||
| + | Powering on as of Dec 2024 # | ||
| + | Uses Cougar Cove P-Cores and Skymont E-Cores, four LPE cores # | ||
| + | Branded "Core Ultra 300 series" # | ||
| + | iGPU features Xe3 "Celestial" graphics architecture # | ||
| + | iGPU with 12 CU # | ||
| + | AI performance doubled # | ||
| + | Uses Intel 18A process # | ||
| + | Doubles the core count over Lunar Lake to 16 cores # | ||
| + | Memory support LPDDR5X exclusively # | ||
| + | Multi-tile configuration of 5 tiles. CPU and NPU in "Die 4", Platform control (PCD) in "Die 1", | ||
| + | iGPU in "Die 5", two other tiles for structural integrity # | ||
| + | Uses Xe3 "Celestial" GPU cores # | ||
| + | Entry-level configs run at 15 W PL1 and 44 W PL2 in baseline mode, | ||
| + | scaling to 25 W PL1 and 55 W PL2 in performance mode # | ||
| + | Possibly increased memory capacities (above 32 GB) # | ||
| + | Panther Lake will be used in future Intel-base handheld gaming PCs # | ||
| + | Thunderbolt 4 supported # | ||
| + | Up to 5.1 GHz, 16 cores, detailed SKU listing here # | ||
| + | Core Ultra X9 388H, Core Ultra X7 368H, Core Ultra 366H, Core Ultra X7 358H, Core Ultra 365, | ||
| + | Core Ultra 386H, Core Ultra 356H, Core Ultra X5 338H, Core Ultra 355, Core Ultra 336H, | ||
| + | Core Ultra 335, Core Ultra 325, Core Ultra 332, Core Ultra 322 # | ||
| + | Core configs: 4P+8E+4LPE, 4P+4E+4LPE, 4P+0E+4LPE, 2P+0E+4LPE # | ||
| + | X7 358H: 20,000 Cinebench, Ultra 5 338H: 16,000 Cinebench # | ||
| + | X7 358H iGPU Performance # | ||
| + | |||
| + | Intel Arrow Lake Refresh [updated] | ||
| + | Release Date: Late 2025 # # | ||
| + | Only for K and KF SKUs # | ||
| + | Could be canceled # | ||
| + | Or resurrected # | ||
| + | Adds NPU inside SOC tile # | ||
| + | 48 TOPS NPU # | ||
| + | 125 W TDP # | ||
| + | Higher clock speeds # | ||
| + | Could be called Core Ultra 300 (and Nova Lake becomes Core Ultra 400) # | ||
| + | Possible naming: Core Ultra 7 270K Plus # | ||
| + | 270K Plus: 8P + 16E, 3.7 GHz base, 5.5 GHz boost # | ||
| + | Other models: Ultra 9 290K Plus, Core Ultra 5 250K # | ||
| + | Socket LGA 1851 # | ||
| + | No changes to NPU, same 11.5 TOPS NPU 3 design # | ||
| + | Another leaks says faster NPU # | ||
| + | |||
| + | Intel Bartlett Lake for Gaming [updated] | ||
| + | Release Date: Unknown # | ||
| + | CPU with 12 P-Cores # | ||
| + | Bartlett Lake is already out for edge and networking applications, could come to gaming segment # | ||
| + | Uses Socket LGA1700 # | ||
| + | No E-Cores # | ||
| + | Might be focused on OEM and embedded markets, not DIY retail # | ||
| + | |||
| + | Intel Twin Lake | ||
| + | Release Date: Unknown # | ||
| + | Successor to "Alder Lake N" # | ||
| + | E-Cores only, using "Skymont" architecture # | ||
| + | |||
| + | Intel Clearwater Forest [updated] | ||
| + | Release Date: H1 2026 # | ||
| + | Intel 18A process # | ||
| + | Uses Direct 3D Stacking technology # | ||
| + | 12 compute chiplets stacked on 3 base tiles # | ||
| + | 288 cores # | ||
| + | Very big chip # | ||
| + | Darkmont E-Core # | ||
| + | Successor to Sierra Forest # | ||
| + | 12-channel memory # | ||
| + | |||
| + | Intel Diamond Rapids | ||
| + | Release Date: 2026 # | ||
| + | Branded as "Xeon 7" # | ||
| + | Up to 192 P-Cores, split across four 48-core tiles | ||
| + | Two SKU ranges: one uses 8-channel DDR5, the other 16-channel DDR5 # | ||
| + | MRDIMM Gen 2 support, 12,800 MT/s # | ||
| + | Panther Cove cores # | ||
| + | 500 W per socket # | ||
| + | Platform: Oak Stream # | ||
| + | 18A process # | ||
| + | Intel APX support # | ||
| + | Native support for TF32 and FP8 # | ||
| + | LGA 9324 # | ||
| + | |||
| + | Intel Griffin Cove | ||
| + | Codename for new P-Core # | ||
| + | Great-grandchild of Lion Cove | ||
| + | Intel Grand Ridge | ||
| + | Release Date: Unknown, could be canceled | ||
| + | Produced on 7 nm HLL+ process | ||
| + | Successor to Atom "Snow Ridge" | ||
| + | 24 cores across 6 clusters with 4 cores each | ||
| + | 4 MB L2 per cluster, plus L3 cache | ||
| + | Uses Gracemont CPU core | ||
| + | Dual-channel DDR5 | ||
| + | PCI Express Gen 4 with 16 lanes | ||
| + | ---- | ||
* Intel Beast Lake | * Intel Beast Lake | ||
Release Date: 2026 or 2027 # | Release Date: 2026 or 2027 # | ||
Revision as of 18:45, 2 January 2026
This page documents Intel's past and future processor roadmaps.
- See also: Intel, Core, Intel Atom, and Lake
Roadmap
- • Roadmap
- Intel Core (P) • Intel Atom (E)
See also
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