Semiconductor & Computer Engineering
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Difference between revisions of "nvidia"
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== Comparison == | == Comparison == | ||
:;Tegra | :;Tegra | ||
| + | |||
{|class="wikitable" style="font-size: 95%; text-align: center;" | {|class="wikitable" style="font-size: 95%; text-align: center;" | ||
|+ | |+ | ||
! colspan="2" |Generation | ! colspan="2" |Generation | ||
!Tegra 2 | !Tegra 2 | ||
| − | !Tegra 3 | + | !Tegra 3 <br>(Kal-El) |
| − | !Tegra 4 | + | !Tegra 4 <br>(Wayne) |
| − | !Tegra 4i | + | !Tegra 4i <br>(Grey) |
| − | ! colspan="2" |Tegra K1 | + | ! colspan="2" |Tegra K1 <br>(Logan) |
| − | !Tegra X1 | + | !Tegra X1 <br>(Erista) |
| − | !Tegra X1+ | + | !Tegra X1+ <br>(Mariko) |
| − | !Tegra X2 | + | !Tegra X2 <br>(Parker) |
| − | !Xavier | + | !{{nvidia|Tegra Xavier|Tegra <br>Xavier}} |
| − | !Orin | + | !Tegra <br>Orin |
| − | !Thor | + | !Tegra <br>Thor |
|- | |- | ||
| − | ! rowspan=" | + | ! rowspan="6" |CPU |
| − | ! | + | !Models |
| − | | | + | | AP25/T25 || T30/<!--T30L<br>AP33/-->T33 || T114 || T148? || T124 || T132 || T210 || T214 || T186 || T194 || T234 || T264? |
| − | | | ||
| − | | | ||
| − | | | ||
|- | |- | ||
!Cores | !Cores | ||
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|2x <br>'''{{nvidia|Denver|l=arch}}''' | |2x <br>'''{{nvidia|Denver|l=arch}}''' | ||
| colspan="2" |4x ARM Cortex-A53 <br>(disabled) +<br>4x ARM Cortex-A57 | | colspan="2" |4x ARM Cortex-A53 <br>(disabled) +<br>4x ARM Cortex-A57 | ||
| − | |2x '''{{nvidia|Denver|l=arch}}'''2 <br>+ 4x ARM <br>Cortex-A57 | + | |2x '''{{nvidia|Denver|l=arch}}''' 2 <br>+ 4x ARM <br>Cortex-A57 |
|8x <br>'''{{nvidia|Carmel|l=arch}}''' | |8x <br>'''{{nvidia|Carmel|l=arch}}''' | ||
|12x <br>Cortex<br>-A78AE | |12x <br>Cortex<br>-A78AE | ||
|'''[[Neoverse]]''' <br>V3AE | |'''[[Neoverse]]''' <br>V3AE | ||
|- | |- | ||
| − | !L1 cache (I/D) | + | !Instruction <br>set |
| + | | colspan="5" |[[ARMv7|ARMv7‑A]] <br>(32‑bit) | ||
| + | | colspan="4" |[[ARMv8|ARMv8‑A]] <br>(64‑bit) | ||
| + | | colspan="2" |[[ARMv8|ARMv8.2‑A]] <br>(64‑bit) | ||
| + | | [[ARMv9|ARMv9.2‑A]] <br>(64‑bit) | ||
| + | |- | ||
| + | !L1 cache <br>(I/D) | ||
| colspan="5" |32/32KB | | colspan="5" |32/32KB | ||
|128/64KB | |128/64KB | ||
| Line 294: | Line 298: | ||
|LPDDR3/ <br>LPDDR4 | |LPDDR3/ <br>LPDDR4 | ||
| colspan="3" |LPDDR4/ <br>LPDDR4X | | colspan="3" |LPDDR4/ <br>LPDDR4X | ||
| − | |LPDDR5 | + | | colspan="2" |LPDDR5 |
| − | |||
|- | |- | ||
!Max. size | !Max. size | ||
Revision as of 05:00, 4 April 2025
| NVIDIA | |
| |
| Type | Public |
| Founded | 1993 |
| Founder | Jen-Hsun Huang Chris Malachowsky Curtis Priem |
| Headquarters | Santa Clara, California |
| Website | http://www.nvidia.com |
NVIDIA Corporation is an American fabless semiconductor company that focuses largely on graphics processing units for the gaming industry and machine learning applications. They also design various other chips, SoC, and consumer electronics for the mobile and automotive markets.
GPU Families
- GeForce 2
- GeForce 2 Go
- GeForce 3
- GeForce 4
- GeForce 4 Go
- GeForce FX
- GeForce FX Go 5
- GeForce 6
- GeForce Go 6
CPU Families
-
- GoForce
- Tegra 2 • AP20H/AP25/T20/T25 (VEC4)
- Tegra 3 (Kal-El) • T30/T30L/T33/AP33
- Tegra 4 (Wayne) • T114 (VEC4)
- Tegra 4i (Grey) • T148? (VEC4)
- Tegra K1 (Logan) • T124 • T132 (Denver)
- Tegra X1 (Erista) • T210 (Maxwell)
- Tegra X1+ (Mariko) • T214 (Maxwell)
- Tegra X2 (Parker) • T186 (Denver 2)
- Tegra Xavier • T194 (Carmel/Volta)
- Tegra Orin • T234 (Hercules) • T239 (Drake)
- Tegra Grace • T241 (Neoverse V2)
- Tegra Thor • T264? (Neoverse V3AE)
Microarchitectures
Comparison
- Tegra
| Generation | Tegra 2 | Tegra 3 (Kal-El) |
Tegra 4 (Wayne) |
Tegra 4i (Grey) |
Tegra K1 (Logan) |
Tegra X1 (Erista) |
Tegra X1+ (Mariko) |
Tegra X2 (Parker) |
Tegra Xavier |
Tegra Orin |
Tegra Thor | ||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| CPU | Models | AP25/T25 | T30/T33 | T114 | T148? | T124 | T132 | T210 | T214 | T186 | T194 | T234 | T264? |
| Cores | 2x ARM Cortex-A9 |
4+1x ARM Cortex-A9 |
4+1x ARM Cortex-A15 |
4+1x ARM Cortex-A9 |
4+1x ARM Cortex-A15 |
2x Denver |
4x ARM Cortex-A53 (disabled) + 4x ARM Cortex-A57 |
2x Denver 2 + 4x ARM Cortex-A57 |
8x Carmel |
12x Cortex -A78AE |
Neoverse V3AE | ||
| Instruction set |
ARMv7‑A (32‑bit) |
ARMv8‑A (64‑bit) |
ARMv8.2‑A (64‑bit) |
ARMv9.2‑A (64‑bit) | |||||||||
| L1 cache (I/D) |
32/32KB | 128/64KB | 32/32KB + 64/32KB |
128/64KB + 48/32KB |
128/64KB | 64/64KB | |||||||
| L2 cache | 1 MB | 2 MB | 128KB + 2MB |
2MB + 2MB |
8 MB | 3 MB | ? | ||||||
| L3 cache | N/A | 4 MB | 6 MB | ? | |||||||||
| GPU | Architecture | Vec4 | Kepler | Maxwell | Pascal | Volta | Ampere | Blackwell | |||||
| CUDA cores | 4+4* | 8+4* | 48+24* | 48+12* | 192 | 256 | 512 | 2048 | ? | ||||
| Tensor cores | N/A | 64 | ? | ||||||||||
| RT cores | N/A | 8 | ? | ||||||||||
| RAM | Protocol | DDR2/ LPDDR2 |
DDR3/ LPDDR2 |
DDR3/ LPDDR3 |
LPDDR3/ LPDDR4 |
LPDDR4/ LPDDR4X |
LPDDR5 | ||||||
| Max. size | 1 GB | 2 GB | 4 GB | 8 GB | 64 GB | 128 GB | |||||||
| Bandwidth | 2.7 GB/s | 6.4 GB/s | 7.5 GB/s | 14.9 GB/s | 25.6 GB/s |
34.1 GB/s |
59.7 GB/s |
136.5 GB/s |
204.8 GB/s |
? | |||
| Process | 40 nm | 28 nm | 20 nm | 16 nm | 12 nm | 8 nm | 4 nm | ||||||
- VLIW-based Vec4: Pixel shaders + Vertex shaders. Since Kepler, Unified shaders are used.
Technology
Facts about "Nvidia"
| company type | public + |
| founded | 1993 + |
| founder | Jen-Hsun Huang +, Chris Malachowsky + and Curtis Priem + |
| full page name | nvidia + |
| headquarters | Santa Clara, California + |
| instance of | semiconductor company + |
| name | NVIDIA + |
| website | http://www.nvidia.com + |
| wikidata id | Q182477 + |