Difference between revisions of "samsung/exynos/8895"

	Edit Values
	Exynos 8895
	General Info
Designer	Samsung,; ARM Holdings
Manufacturer	Samsung
Model Number	8895
Market	Mobile
Introduction	February 23, 2017 (announced); March 29, 2017 (launched)
	General Specs
Family	Exynos
Series	Exynos 9
Locked	No
Frequency	2314 MHz, 1690 MHz
Turbo Frequency	2808 MHz
Turbo Frequency	2002 MHz (1 core),; 2002 MHz (2 cores),; 2002 MHz (3 cores),; 2002 MHz (4 cores),; 2808 MHz (5 cores),; 2808 MHz (6 cores),; 2808 MHz (7 cores),; 2808 MHz (8 cores)
Bus type	exynos-ossclk (Exynos SoC Base Clock)
Bus speed	26MHz
Bus rate	3? × 8GT/s
Clock multiplier	23x - 28x (turbo)
CPUID	universal8895
	Microarchitecture
ISA	ARMv8 (ARM)
Microarchitecture	M2, Cortex-A53
Platform	universal8895
Chipset	Exynos 8895
Core Name	Mongoose 2, Cortex-A53
Core Family	Samsung Mongoose, ARM Cortex
Core Model	Samsung Mongoose 2, Cortex A53
Process	10 nm
Technology	CMOS
MCP	No
Word Size	64 bit
Cores	8
Threads	8
Max Memory	8 GiB
	Multiprocessing
Max SMP	1-Way (Uniprocessor)
	Electrical
Vcore	0.7 V-1.3 V
VI/O	1.02 V
TDP	8 W
cTDP down	8 W
cTDP down frequency	2314 MHz
cTDP up	16 W
cTDP up frequency	2808 MHz
OP Temperature	-15 °C – 115 °C
Tjunction	110 – 115
	Succession
	Exynos 8890 Exynos 9810
	Contemporary
	Exynos 9820

Latest revision as of 02:25, 17 March 2025

Exynos 8895 is a 64-bit octa-core ARM high performance mobile system on a chip designed by Samsung and introduced in mid-2017. The processor is fabricated on Samsung's 10nm EUV (Extreme Ultra Violet) FinFET process and features 8 cores in a dual-cluster configuration consisting of 4 Mongoose 2 big cores commonly running at 2314 (but can go up to 2808 MHz with Turbo unlocked), 4 Cortex-A53 little cores at 1690 (Can go up to 2002 MHz with Turbo unlocked). This chip supports up to 8 GiB of dual-channel 16-bit LPDDR4X-1796 memory and incorporates a Mali-G71 MP20 GPU running at 546MHz (But can go up to 839MHz with turbo unlocked). The 8895 incorporates an LTE modem supporting cat 16 download and upload.

Exynos Turbo[edit]

As far as we know, Turbo frequencies are actually frequencies that the Exynos 8895 could originally go to, but it was limited most likely due to the heating that the Exynos were suffering at the time.

Exynos ossclk[edit]

The exynos-ossclk is responsible for generating the base frequency for components such as (cpu, gpu, ram, bus, dsp, madera, mif) and also for components outside the SoC like (usb, wifi, camera, pcie).

rate : 26MHz

Exynos MIF[edit]

MIF is basically the RAM controller its frequency must be parallel with the ram frequency.

rate : 1794MHz

DSP Devfreq[edit]

DSP is responsible for managing the connection speed between the display and the GPU.

If the DSP frequency is manually manipulated by the user, it will be possible to notice a difference in the fluidity of the display, the change in the maximum and minimum DSP frequencies will alter the data transfer rate sent to the display.

Madera Devfreq[edit]

Madera is the audio controller chip for the Exynos 8895.

The User manipulation of the Madera frequency may increase or decrease the latency of the speaker audio.

Cache[edit]

Main articles: Mongoose 2 § Cache and Cortex-A53 § Cache

For the Mongoose 2 core cluster:

[Edit/Modify Cache Info]

Cache Organization

Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.

L1$

192 KiB

196,608 B
0.188 MiB

L1I$	128 KiB 131,072 B 0.125 MiB	2x64 KiB	4-way set associative
L1D$	64 KiB 65,536 B 0.0625 MiB	2x32 KiB	8-way set associative

L2$

1 MiB

1,024 KiB
1,048,576 B
9.765625e-4 GiB

		2x512 KiB	16-way set associative

L3$

2 MiB

2,048 KiB
2,097,152 B
0.00195 GiB

		2x1 MiB

For the Cortex-A53 cluster:

[Edit/Modify Cache Info]

Cache Organization

Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.

L1$

256 KiB

262,144 B
0.25 MiB

L1I$	128 KiB 131,072 B 0.125 MiB	2x64 KiB	4-way set associative
L1D$	128 KiB 131,072 B 0.125 MiB	2x64 KiB	16-way set associative

L2$

512 KiB

0.5 MiB
524,288 B
4.882812e-4 GiB

		2x256 KiB	8-way set associative

Memory controller[edit]

[Edit/Modify Memory Info]

Integrated Memory Controller

Max Type	LPDDR4X-1796
Supports ECC	No
Max Mem	8 GiB
Frequency	1796 MHz
Controllers	2
Channels	2
Width	32 bit
Max Bandwidth	28.70 GB/s 26.729 GiB/s 27,370.453 MiB/s 28,700 MB/s 0.0261 TiB/s 0.0287 TB/s
Bandwidth	Single 14.32 GB/s Double 28.64 GB/s

Graphics[edit]

[Edit/Modify IGP Info]

Integrated Graphics Information

GPU

Mali-G71

Designer

ARM Holdings

Execution Units

20

Max Displays

2

Frequency

546 MHz

0.546 GHz
546,000 KHz

Burst Frequency

839 MHz (turbo)

"MHz(turbo)" is not declared as a valid unit of measurement for this property.

Output

DSI

Max Resolution

HDMI	2850x1440 @60Hz

Standards

DirectX	12
OpenCL	2.0
OpenGL ES	3.2
OpenVG	1.1
Vulkan	1.1

Codec	Encode	Decode150
HEVC (H.265)	✔	✔
MPEG-4 AVC (H.264)	✔	✔
VP9	✔	✔

All at 4K UHD 60fps.

Wireless[edit]

Wireless Communications

Cellular

4G

LTE Advanced

UE Cat DL	16 (1000 Mbps)
UE Cat UL	16 (280 Mbps)

ISP[edit]

28MP Rear
16MP Front
28MP+28MP Dual

Features[edit]

[Edit/Modify Supported Features]

Supported ARM Extensions & Processor Features

NEON	Advanced SIMD extension
TrustZone	TrustZone Security Extensions
CRC32	CRC-32 checksum Extension
Crypto	Cryptographic Extension
FP	Floating-point Extension

Utilizing devices[edit]

Samsung Galaxy Note 8
Samsung Galaxy S8
Samsung Galaxy S8+

@@ Line 15: / Line 15: @@
 |frequency=2314 MHz
 |frequency 2=1690 MHz
-|turbo frequency1=1690 MHz
+|turbo frequency1=2002 MHz
-|turbo frequency2=1690 MHz
+|turbo frequency2=2002 MHz
-|turbo frequency3=1690 MHz
+|turbo frequency3=2002 MHz
-|turbo frequency4=1690 MHz
+|turbo frequency4=2002 MHz
-|turbo frequency5=2314 MHz
+|turbo frequency5=2808 MHz
-|turbo frequency6=2314 MHz
+|turbo frequency6=2808 MHz
-|turbo frequency7=2314 MHz
+|turbo frequency7=2808 MHz
-|turbo frequency8=2314 MHz
+|turbo frequency8=2808 MHz
 |turbo frequency 2=2002 MHz
 |turbo frequency=2808 MHz
-|bus type=exynos-ossclk (FSB)
+|bus type=exynos-ossclk (Exynos SoC Base Clock)
 |bus speed=26MHz
 |bus links=3?
 |bus rate=8GT/s
-|clock multiplier=108
+|clock multiplier=23x - 28x (turbo)
 |cpuid=universal8895
 |isa=ARMv8
@@ Line 71: / Line 71: @@
 |contemporary link=samsung/exynos/9820
 }}
-'''Exynos 8895''' is a {{arch|64}} [[octa-core]] [[ARM]] high performance mobile [[system on a chip]] designed by [[Samsung]] and introduced in mid-[[2017]]. The processor is fabricated on Samsung's [[10 nm process|10nm]] EUV (Extreme Ultra Violet) FinFET process and features [[8 cores]] in a dual-cluster configuration consisting of 4 {{samsung|Mongoose 2|l=arch}} [[big cores]] commonly running at 2314 (but can go up to 2808 MHz), 4 {{armh|Cortex-A53|l=arch}} [[little cores]] at 1690 (to 2002 MHz). This chip supports up to 8 GiB of dual-channel 16-bit LPDDR4X-1796 memory and incorporates a {{armh|Mali-G71}} MP20 GPU running at 546MHz. The 8895 incorporates an LTE modem supporting cat 16 download and upload.
+'''Exynos 8895''' is a {{arch|64}} [[octa-core]] [[ARM]] high performance mobile [[system on a chip]] designed by [[Samsung]] and introduced in mid-[[2017]]. The processor is fabricated on Samsung's [[10 nm process|10nm]] EUV (Extreme Ultra Violet) FinFET process and features [[8 cores]] in a dual-cluster configuration consisting of 4 {{samsung|Mongoose 2|l=arch}} [[big cores]] commonly running at 2314 (but can go up to 2808 MHz with Turbo unlocked), 4 {{armh|Cortex-A53|l=arch}} [[little cores]] at 1690 (Can go up to 2002 MHz with Turbo unlocked). This chip supports up to 8 GiB of dual-channel 16-bit LPDDR4X-1796 memory and incorporates a {{armh|Mali-G71}} MP20 GPU running at 546MHz (But can go up to 839MHz with turbo unlocked). The 8895 incorporates an LTE modem supporting cat 16 download and upload.
+== Exynos Turbo ==
+As far as we know, Turbo frequencies are actually frequencies that the Exynos 8895 could originally go to, but it was limited most likely due to the heating that the Exynos were suffering at the time.
+== Exynos ossclk ==
+ The exynos-ossclk is responsible for generating the base frequency for components such as (cpu, gpu, ram, bus, dsp, madera, mif) and also for components outside the SoC like (usb, wifi, camera, pcie).
+rate : 26MHz
+== Exynos MIF ==
+ MIF is basically the RAM controller its frequency must be parallel with the ram frequency.
+rate : 1794MHz
+== DSP Devfreq ==
+DSP is responsible for managing the connection speed between the display and the GPU.
+If the DSP frequency is manually manipulated by the user, it will be possible to notice a difference in the fluidity of the display, the change in the maximum and minimum DSP frequencies will alter the data transfer rate sent to the display.
+== Madera Devfreq ==
+Madera is the audio controller chip for the Exynos 8895.
+The User manipulation of the Madera frequency may increase or decrease the latency of the speaker audio.
 == Cache ==
@@ Line 115: / Line 139: @@
 |width=32 bit
 |max bandwidth=28.70 GB/s
-|frequency=1794 MHz
+|frequency=1796 MHz
 |bandwidth schan=14.32 GB/s
 |bandwidth dchan=28.64 GB/s
@@ Line 129: / Line 153: @@
 | max memory          =
 | frequency           = 546 MHz
-| max frequency       = 839 MHz
+| max frequency       = 839 MHz (turbo)
 | output crt          =
@@ Line 136: / Line 160: @@
 | output edp          =
 | output dp           =
-| output hdmi         =
+| output hdmi         = Yes (Dex)
 | output vga          =
 | output dvi          =
@@ Line 144: / Line 168: @@
 | opengl es ver      = 3.2
 | openvg ver         = 1.1
-| opencl ver         = 2
+| opencl ver         = 2.0
-| vulkan ver         = 1.0
+| vulkan ver         = 1.1
 | hdmi ver           =
 | dp ver             =
 | edp ver            =
-| max res hdmi       =
+| max res hdmi       = 2850x1440
-| max res hdmi freq  =
+| max res hdmi freq  = 60Hz
 | max res dp         =
 | max res dp freq    =
@@ Line 224: / Line 248: @@
 |vfpv5=No
 |neon=Yes
-|trustzone=No
+|trustzone=Yes
 |jazelle=No
 |wmmx=No

base frequency	2,314 MHz (2.314 GHz, 2,314,000 kHz) + and 1,690 MHz (1.69 GHz, 1,690,000 kHz) +
bus rate	8,000 MT/s (8 GT/s, 8,000,000 kT/s) +
bus speed	26 MHz (0.026 GHz, 26,000 kHz) +
bus type	exynos-ossclk (Exynos SoC Base Clock) +
chipset	Exynos 8895 +
core count	8 +
core family	Samsung Mongoose + and ARM Cortex +
core model	Samsung Mongoose 2 + and Cortex A53 +
core name	Cortex-A53 + and Mongoose 2 +
core voltage (max)	1.3 V (13 dV, 130 cV, 1,300 mV) +
core voltage (min)	0.7 V (7 dV, 70 cV, 700 mV) +
cpuid	universal8895 +
designer	Samsung + and ARM Holdings +
family	Exynos +
first announced	February 23, 2017 +
first launched	March 29, 2017 +
full page name	samsung/exynos/8895 +
has 4g support	true +
has ecc memory support	false +
has locked clock multiplier	false +
has lte advanced support	true +
instance of	microprocessor +
integrated gpu	Mali-G71 +
integrated gpu base frequency	546 MHz (0.546 GHz, 546,000 KHz) +
integrated gpu designer	ARM Holdings +
integrated gpu execution units	20 +
io voltage	1.02 V (10.2 dV, 102 cV, 1,020 mV) +
is multi-chip package	false +
isa	ARMv8 +
isa family	ARM +
l1$ size	192 KiB (196,608 B, 0.188 MiB) + and 256 KiB (262,144 B, 0.25 MiB) +
l1d$ description	8-way set associative + and 16-way set associative +
l1d$ size	64 KiB (65,536 B, 0.0625 MiB) + and 128 KiB (131,072 B, 0.125 MiB) +
l1i$ description	4-way set associative +
l1i$ size	128 KiB (131,072 B, 0.125 MiB) +
l2$ description	16-way set associative + and 8-way set associative +
l2$ size	1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) + and 0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) +
l3$ size	2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) +
ldate	March 29, 2017 +
manufacturer	Samsung +
market segment	Mobile +
max cpu count	1 +
max junction temperature	115 K (-158.15 °C, -252.67 °F, 207 °R) +
max memory	8,192 MiB (8,388,608 KiB, 8,589,934,592 B, 8 GiB, 0.00781 TiB) +
max memory bandwidth	26.729 GiB/s (27,370.453 MiB/s, 28.7 GB/s, 28,700 MB/s, 0.0261 TiB/s, 0.0287 TB/s) +
max memory channels	2 +
max operating temperature	115 °C +
microarchitecture	Cortex-A53 + and M2 +
min junction temperature	110 K (-163.15 °C, -261.67 °F, 198 °R) +
min operating temperature	-15 °C +
model number	8895 +
name	Exynos 8895 +
platform	universal8895 +
process	10 nm (0.01 μm, 1.0e-5 mm) +
series	Exynos 9 +
smp max ways	1 +
supported memory type	LPDDR4X-1796 +
tdp	8 W (8,000 mW, 0.0107 hp, 0.008 kW) +
tdp down	8 W (8,000 mW, 0.0107 hp, 0.008 kW) +
tdp down frequency	2,314 MHz (2.314 GHz, 2,314,000 kHz) +
tdp up	16 W (16,000 mW, 0.0215 hp, 0.016 kW) +
tdp up frequency	2,808 MHz (2.808 GHz, 2,808,000 kHz) +
technology	CMOS +
thread count	8 +
turbo frequency	2,808 MHz (2.808 GHz, 2,808,000 kHz) +
turbo frequency (1 core)	2,002 MHz (2.002 GHz, 2,002,000 kHz) +
turbo frequency (2 cores)	2,002 MHz (2.002 GHz, 2,002,000 kHz) +
turbo frequency (3 cores)	2,002 MHz (2.002 GHz, 2,002,000 kHz) +
turbo frequency (4 cores)	2,002 MHz (2.002 GHz, 2,002,000 kHz) +
turbo frequency (5 cores)	2,808 MHz (2.808 GHz, 2,808,000 kHz) +
turbo frequency (6 cores)	2,808 MHz (2.808 GHz, 2,808,000 kHz) +
turbo frequency (7 cores)	2,808 MHz (2.808 GHz, 2,808,000 kHz) +
turbo frequency (8 cores)	2,808 MHz (2.808 GHz, 2,808,000 kHz) +
used by	Samsung Galaxy Note 8 +, Samsung Galaxy S8 + and Samsung Galaxy S8+ +
user equipment category downlink	16 +
user equipment category uplink	16 +
word size	64 bit (8 octets, 16 nibbles) +

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