Revision as of 16:20, 23 February 2025

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Snapdragon 855
General Info
Designer	Qualcomm, ARM Holdings
Manufacturer	TSMC
Model Number	SDM855
Part Number	SM8150
Market	Mobile
Introduction	December 4, 2018 (announced) March, 2019 (launched)
General Specs
Family	Snapdragon 800, Snapdragon 8
Series	800
Frequency	1.8 GHz, 2.42 GHz, 2.84 GHz
Microarchitecture
ISA	ARMv8 (ARM)
Microarchitecture	Cortex-A76, Cortex-A55
Core Name	Kryo 485 Gold, Kryo 485 Silver, Kryo 485 Prime
Process	7 nm
Transistors	6,700,000,000
Technology	CMOS
Die	73.27 mm² 8.48 mm × 8.64 mm
Word Size	64 bit
Cores	8
Threads	8
Max Memory	16 GiB
Multiprocessing
Max SMP	1-Way (Uniprocessor)
Packaging
Succession
Snapdragon 845 Snapdragon 865
Contemporary
Snapdragon 855+/860

Block Diagram

Snapdragon 855 is a high-performance 64-bit ARM LTE system on a chip designed by Qualcomm and introduced in late 2018.

Fabricated on TSMC 7nm process, the 855 features four Kryo 485 Silver high-efficiency cores operating at 1.8 GHz along with three high-performance Kryo 485 Gold operating at 2.42 GHz and another higher-performance Kryo 485 Prime core operating at 2.84 GHz.

The Snapdragon 855 integrates the Adreno 640 GPU operation at 585 MHz and features an X24 LTE modem supporting Cat 20 uplink and Cat 20 downlink. This chip supports up to 16 GiB of quad-channel LPDDR4X-4266 memory.

The Snapdragon 855 can be paired with Qualcomm's X50 5G modem (an external chip) and an RF front-end interface chip (RFFE) to bring 5G NR, sub-6 GHz and mmWave, support.

The 855 Plus is an identical, but higher clocked version of this processor.

Clock domains

See also: TSMC 7-nanometer (N7) process technology

The Snapdragon 855 utilizes TSMC 7-nanometer process. One of the major changes Qualcomm has done compared to the Snapdragon 845 is on the physical implementation side. Whereas the Snapdragon 845 uses two clock domains in a standard DynamIQ cluster - one for the Silver cores and one for the Gold cores, the 855 uses three clock domains. One of the cores from the prior quad-core Gold clock domains has been moved to its own clock domain. Qualcomm refers to that core as a 'Prime' core. The Prime core utilizes TSMC high-performance cell (which uses a slightly relaxed 64 nm poly pitch) while the rest of the SoC utilizes TSMC standard high-density cells. The use of the high-performance cells allows for the slightly higher frequency at similar power.

Qualcomm reported that at the same power, Clock2 CPUs have improved by roughly 20% from the SDM845 to the SDM855. With the addition of Clock3, the four cores collectively extend this performance gain over the quad-core cluster on the 845 to over 30%. Check New Qualcomm Snapdragon 8 gen 1 vs A15 Bionic Comparison

Cache

Main articles: Cortex-A76 § Cache and Cortex-A55 § Cache

Prime core Cortex-A76:

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 128 KiB 131,072 B 0.125 MiB L1I$ 64 KiB 65,536 B 0.0625 MiB 1x64 KiB 4-way set associative   L1D$ 64 KiB 65,536 B 0.0625 MiB 1x64 KiB 4-way set associative   L2$ 512 KiB 0.5 MiB 524,288 B 4.882812e-4 GiB     1x512 KiB 8-way set associative

3 core cluster Cortex-A76:

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 384 KiB 393,216 B 0.375 MiB L1I$ 192 KiB 196,608 B 0.188 MiB 3x64 KiB 4-way set associative   L1D$ 192 KiB 196,608 B 0.188 MiB 3x64 KiB 4-way set associative   L2$ 768 KiB 0.75 MiB 786,432 B 7.324219e-4 GiB     3x256 KiB 8-way set associative

Quad-core cluster Cortex-A55:

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 512 KiB 524,288 B 0.5 MiB L1I$ 256 KiB 262,144 B 0.25 MiB 4x64 KiB 2-way set associative   L1D$ 256 KiB 262,144 B 0.25 MiB 4x64 KiB 4-way set associative   L2$ 512 KiB 0.5 MiB 524,288 B 4.882812e-4 GiB     4x128 KiB 8-way set associative

• 2 MiB L3

Memory controller

[Edit/Modify Memory Info]

	Integrated Memory Controller
	Max Type LPDDR4X-4266 Supports ECC No Max Mem 16 GiB Frequency 2133 MHz Controllers 1 Channels 4 Width 16 bit Max Bandwidth 31.79 GiB/s 32,552.96 MiB/s 34.134 GB/s 34,134.253 MB/s 0.031 TiB/s 0.0341 TB/s Bandwidth Single 7.95 GiB/s Double 15.89 GiB/s Quad 31.79 GiB/s

DSP

This chip features Qualcomm's Hexagon 690 DSP.

Graphics

[Edit/Modify IGP Info]

	Integrated Graphics Information
	GPU Adreno 640 GPU Designer Qualcomm Execution Units 2 (384x 2 ALU) "(384x2ALU)" can not be assigned to a declared number type with value 2. Max Displays 2 Frequency 257 MHz 0.257 GHz 257,000 KHz Burst Frequency 585 MHz 0.585 GHz 585,000 KHz Standards DirectX 12 OpenCL 2.0 OpenGL ES 3.2 Vulkan 1.1

• Codec: H.265 (HEVC), H.264 (AVC), HDR10, HDR10+, HLG, VP8, VP9
• HDR Playback Codec support for HDR10+, HDR10, HLG and Dolby Vision
• Volumetric VR video playback
• 8K 360 VR video playback

Camera

• ISP
  • Qualcomm Spectra 380 image signal processor
    • Dual 14-bit CV-ISPs
    • Hardware accelerator for computer vision (CV-ISP)
  • Up to 20 MP dual camera
  • Up to 48 MP single camera

• Photo Capture: HEIF photo capture
• Video Capture:
  • Rec. 2020 color gamut video capture
  • Up to 10-bit color depth video capture
  • Slow motion video capture up to 720p at 480fps,HEVC Video Capture

Connectivity

• X24 LTE modem
  • LTE Category 20
  • Downlink:
    • 2 Gbps peak
    • 7x20 MHz carrier aggregation
    • Up to 256-QAM
    • Up to 4x4 MIMO on five carriers
    • Full-Dimension MIMO (FD-MIMO)
    • Maximum 20 spatial streams
  • Uplink:
    • 316 Mbps peak
    • 3x20 MHz carrier aggregation
    • Up to 2x 106Mbps LTE streams
    • Up to 256-QAM
    • Uplink data compression
• LTE FDD, LTE TDD including CBRS support, LAA, LTE Broadcast, WCDMA (DB-DC-HSDPA, DC-HSUPA), TD-SCDMA, CDMA 1x, EV-DO, GSM/EDGE

• WiFi
  • Standards: 802.11ax, 802.11ac Wave 2, 802.11a/b/g, 802.11n
  • Spectral Bands: 2.4 GHz, 5 GHz

• Bluetooth
  • Bluetooth 5.0
  • 2 Mbps

Location

• Systems: GPS, GLONASS, Beidou, Galileo, QZSS, SBAS, Dual frequency GNSS

Utilizing devices

This list is incomplete; you can help by expanding it.

Documents

• Product Brief
• Entertainment Deep Dive Presentation
• Deep Dive Presentation

Bibliography

• Qualcomm, TSMC, 2019 Symposia on VLSI Technology and Circuits (VLSI 2019).
• Techinsights "Lenovo Brings the New Snapdragon to Market"
• WikiChip Fuse "TSMC 7nm HD and HP Cells, 2nd Gen 7nm, And The Snapdragon 855 DTCO"