-
WikiChip
WikiChip
-
Architectures
Popular x86
-
Intel
- Client
- Server
- Big Cores
- Small Cores
-
AMD
Popular ARM
-
ARM
- Server
- Big
- Little
-
Cavium
-
Samsung
-
-
Chips
Popular Families
-
Ampere
-
Apple
-
Cavium
-
HiSilicon
-
MediaTek
-
NXP
-
Qualcomm
-
Renesas
-
Samsung
-
From WikiChip
Difference between revisions of "Template:interconnect arch"
m (Reverted edits by 195.154.255.194 (talk) to last revision by David) |
(align order of images with NoC and System Bus) |
||
Line 5: | Line 5: | ||
<tr><td class="header" colspan="2">Concepts</td></tr> | <tr><td class="header" colspan="2">Concepts</td></tr> | ||
<tr><td colspan="2"> | <tr><td colspan="2"> | ||
+ | * [[Network On A Chip]] | ||
* [[System Bus]] | * [[System Bus]] | ||
− | |||
</td></tr> | </td></tr> | ||
<tr><td class="header" colspan="2">General</td></tr> | <tr><td class="header" colspan="2">General</td></tr> |
Latest revision as of 09:14, 1 July 2024
v · d · e | |
Interconnect Architectures | |
Concepts | |
General | |
Peripheral | |
Storage Devices | |
Audio Devices | |