Latest revision as of 18:48, 13 September 2022

Comet Lake (CML) is Intel's successor to Coffee Lake, an enhanced 14 nm process microarchitecture for mainstream desktops and mobile devices.

For desktop and mobile, Comet Lake is branded as 10th Generation Intel Core i3, Core i5, Core i7, and Core i9 processors.

Codenames[edit]

Brands[edit]

Intel has released Comet Lake under 4 main brand families:

Logo	Family	General Description	Differentiating Features
			Cores	HT	AVX	AVX2	TBT	ECC
	Core i3	Low-end Performance	Quad	✔	✔	✔	✔	✘
	Core i5	Mid-range Performance	Hexa	✔	✔	✔	✔	✘
	Core i7	High-end Performance	Octa	✔	✔	✔	✔	✘
50px	Core i9	Ultra Performance	Deca	✔	✔	✔	✔	✘

Release Dates[edit]

Comet Lake processors were introduced in a number of phases. Initial mobile processors were launched on August 21, 2019. Intel followed up with the remaining desktop parts on April 30, 2020. Enterprise and vPro models were followed on May 13, 2020.

Compatibility[edit]

There are no official drivers by Intel for Windows 7 or Windows 8. Microsoft announced that only Windows 10 will have support for Kaby Lake. Linux added initial support for Kaby Lake starting with Linux Kernel 4.5.

Compiler support[edit]

CPUID[edit]

Further information: Intel CPUIDs

Architecture[edit]

Key changes from Coffee Lake[edit]

• Enhanced "14nm++" process results in higher turbo frequencies

• System Architecture
  • 25% more cores (up to 10, from 8)
  • 25% more last level cache (up to 20 MiB, up from 16 MiB)

• Chipset
  • 300 Series chipset → 400 Series chipset
    • 2.5G Ethernet (Foxville) support
    • IntegratedWiFi 6 AX201 (GiG+) support via CNVi

• Memory
  • Faster memory for mainstream desktops (i.e., Comet Lake S) DDR4-2933 (from DDR4-2666)

• Graphics
  • Gen 9.5 GPUs (No Change)

• Packaging
  • Die thinning on top-end SKUs for better heat removal

This list is incomplete; you can help by expanding it.

Block Diagram[edit]

This section is empty; you can help add the missing info by editing this page.

Gen9.5[edit]

See Gen9.5#Gen9.5.

Memory Hierarchy[edit]

The overall memory structure is identical to Skylake.

• Cache
  • L0 µOP cache:
    • 1,536 µOPs, 8-way set associative
      • 32 sets, 6-µOP line size
      • statically divided between threads, per core, inclusive with L1I
  • L1I Cache:
    • 32 KiB, 8-way set associative
      • 64 sets, 64 B line size
      • shared by the two threads, per core
  • L1D Cache:
    • 32 KiB, 8-way set associative
    • 64 sets, 64 B line size
    • shared by the two threads, per core
    • 4 cycles for fastest load-to-use (simple pointer accesses)
      • 5 cycles for complex addresses
    • 64 B/cycle load bandwidth
    • 32 B/cycle store bandwidth
    • Write-back policy
  • L2 Cache:
    • Unified, 256 KiB, 4-way set associative
    • Non-inclusive
    • 1024 sets, 64 B line size
    • 12 cycles for fastest load-to-use
    • 64 B/cycle bandwidth to L1$
    • Write-back policy
  • L3 Cache/LLC:
    • Up to 2 MiB Per core, shared across all cores
    • Up to 16-way set associative
    • Inclusive
    • 64 B line size
    • Write-back policy
    • Per each core:
      • Read: 32 B/cycle (@ ring clock)
      • Write: 32 B/cycle (@ ring clock)
    • 42 cycles for fastest load-to-use
  • Side Cache:
    • 64 MiB & 128 MiB eDRAM
    • Per package
    • Only on the Iris Pro GPUs
    • Read: 32 B/cycle (@ eDRAM clock)
    • Write: 32 B/cycle (@ eDRAM clock)
  • System DRAM:
    • 2 Channels
    • 8 B/cycle/channel (@ memory clock)
    • 42 cycles + 51 ns latency

Coffee Lake TLB consists of dedicated L1 TLB for instruction cache (ITLB) and another one for data cache (DTLB). Additionally there is a unified L2 TLB (STLB).

• TLBs:
  • ITLB
    • 4 KiB page translations:
      • 128 entries; 8-way set associative
      • dynamic partitioning
    • 2 MiB / 4 MiB page translations:
      • 8 entries per thread; fully associative
      • Duplicated for each thread
  • DTLB
    • 4 KiB page translations:
      • 64 entries; 4-way set associative
      • fixed partition
    • 2 MiB / 4 MiB page translations:
      • 32 entries; 4-way set associative
      • fixed partition
    • 1G page translations:
      • 4 entries; 4-way set associative
      • fixed partition
  • STLB
    • 4 KiB + 2 MiB page translations:
      • 1536 entries; 12-way set associative
      • fixed partition
    • 1 GiB page translations:
      • 16 entries; 4-way set associative
      • fixed partition

• Note: STLB is incorrectly reported as "6-way" by CPUID leaf 2 (EAX=02H). Coffee Lake erratum CFL084 recommends software to simply ignore that value.

Overview[edit]

This section is empty; you can help add the missing info by editing this page.

Configurability[edit]

This section is empty; you can help add the missing info by editing this page.

Graphics[edit]

This section is empty; you can help add the missing info by editing this page.

Die[edit]

This section is empty; you can help add the missing info by editing this page.

All Comet Lake Chips[edit]