From WikiChip
Difference between revisions of "arm holdings/microarchitectures/chaberton"
< arm holdings

(Chaberton)
 
(No difference)

Latest revision as of 13:16, 4 July 2022

Edit Values
Chaberton µarch
General Info
Arch TypeCPU
DesignerARM Holdings
ManufacturerTSMC
Introduction2024
Process7 nm, 5 nm
Core Configs1, 2, 4
Pipeline
OoOEYes
SpeculativeYes
Reg RenamingYes
Succession

Chaberton is the successor to Hunter, a low-power high-performance synthesizable ARM microarchitecture designed by ARM for the mobile market.


Symbol version future.svg Preliminary Data! Information presented in this article deal with future products, data, features, and specifications that have yet to be finalized, announced, or released. Information may be incomplete and can change by final release.
Retrieved from "https://en.wikichip.org/w/index.php?title=arm_holdings/microarchitectures/chaberton&oldid=100276"
Facts about "Chaberton - Microarchitectures - ARM"
RDF feed
codenameChaberton +
core count1 +, 2 + and 4 +
designerARM Holdings +
first launched2024 +
full page namearm holdings/microarchitectures/chaberton +
instance ofmicroarchitecture +
manufacturerTSMC +
microarchitecture typeCPU +
nameChaberton +
process7 nm (0.007 μm, 7.0e-6 mm) + and 5 nm (0.005 μm, 5.0e-6 mm) +