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Difference between revisions of "amd/microarchitectures/zen 5"
| Line 18: | Line 18: | ||
|cores 11=32 | |cores 11=32 | ||
|cores 12=28 | |cores 12=28 | ||
| − | |cores 13= | + | |cores 13=36 |
| − | |cores 14= | + | |cores 14=24 |
| − | |cores 15= | + | |cores 15=18 |
| − | |cores 16= | + | |cores 16=12 |
|processing elements=256 | |processing elements=256 | ||
|processing elements 2=224 | |processing elements 2=224 | ||
| Line 52: | Line 52: | ||
|predecessor=Zen 4 | |predecessor=Zen 4 | ||
|predecessor link=amd/microarchitectures/zen 4 | |predecessor link=amd/microarchitectures/zen 4 | ||
| + | |successor=Zen 6 or maybe a completely new microarchitecture | ||
|succession=Yes | |succession=Yes | ||
}} | }} | ||
Revision as of 11:09, 24 December 2021
| Edit Values | |
| Zen 5 µarch | |
| General Info | |
| Arch Type | CPU |
| Designer | AMD |
| Manufacturer | TSMC or Samsung |
| Process | 3 nm |
| Core Configs | 256, 224, 192, 144, 128, 96, 72, 64, 56, 48, 32, 28, 36, 24, 18, 12 |
| PE Configs | 256, 224, 384, 288, 256, 192, 144, 128, 112, 96, 64, 56, 60, 40, 30, 20 |
| Pipeline | |
| Type | Superscalar |
| OoOE | Yes |
| Speculative | Yes |
| Reg Renaming | Yes |
| Instructions | |
| ISA | x86-64, AVX512, AMX (Advanced Matrix Extensions) |
| Cores | |
| Core Names | Turin (EPYC server multiprocessor), Da Vinci (Threadripper Workstation), Granite Ridge (Gaming Desktop CPU), Strix Point (Gaming APU with RDNA3 or RDNA4) |
| Succession | |
Zen 5 is a planned microarchitecture being developed by AMD as a successor to Zen 4.
Contents
History
Zen 5 was first mentioned by lead architect Michael Clark during a discussion on April 9th, 2018[1].
Process Technology
Zen 5 is speculated to be produced on a 5nm process.
Codenames
 |
This section is empty; you can help add the missing info by editing this page. |
Architecture
Nothing is currently known about the architectural improvements that are being done to Zen 5.
Key changes from Zen 4
| |
This section is empty; you can help add the missing info by editing this page. |
Designers
- David Suggs, chief architect
Bibliography
See Also
- AMD Zen
- Intel Meteor Lake
Facts about "Zen 5 - Microarchitectures - AMD"
| codename | Zen 5 + |
| core count | 256 +, 224 +, 192 +, 144 +, 128 +, 96 +, 72 +, 64 +, 56 +, 48 +, 32 + and 28 + |
| designer | AMD + |
| full page name | amd/microarchitectures/zen 5 + |
| instance of | microarchitecture + |
| instruction set architecture | x86-64 + and AVX512, AMX (Advanced Matrix Extensions) + |
| manufacturer | TSMC or Samsung + |
| microarchitecture type | CPU + |
| name | Zen 5 + |
| process | 3 nm (0.003 μm, 3.0e-6 mm) + |
| processing element count | 256 +, 224 +, 384 +, 288 +, 192 +, 144 +, 128 +, 112 +, 96 +, 64 +, 56 +, 60 +, 40 +, 30 + and 20 + |